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參數(shù)資料
| 型號： | LC651431F |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Four-Bit CMOS Microcontrollers for Small-Scale Control Applications |
| 中文描述： | 4位CMOS微控制器的小規(guī)?？刂浦械膽?yīng)用 |
| 文件頁數(shù)： | 24/39頁 |
| 文件大小： | 374K |
| 代理商： | LC651431F |
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No. 6498-24/39
LC651432N/F/L, 651431N/F/L
Continued from preceding page.
Parameter
Symbol
Conditions
Applicable pins
Ratings
Unit
min
typ
max
Oscillator characteristics
Ceramic oscillator
Oscillator frequency
Oscillator stabilization time
*
8
f
CFOSC
Figure 2, fo = 4 MHz
*
7
OSC1, OSC2
3920
4000
4080
kHz
t
CFS
Figure 3, fo = 4 MHz
10
ms
Output n-channel
transistors off
V
IN
= V
SS
, V
DD
= 5 V
V
IN
= V
SS
, V
DD
= 5 V
Ports with built-in pull-up
resistor specifications
Built-in pull-up resistor I/O ports
RES
RPP
8
14
30
k
Ru
RES
200
500
800
k
External reset characteristics
Reset time
t
RST
See figure 4.
f = 1 MHz
With all pins except the pin
being tested at V
IN
= V
SS
.
Pin capacitance
Cp
10
pF
Serial clock
Input clock cycle time
t
CKCY
(1)
See figure 5.
SCK
2.0
μs
Output clock cycle time
t
CKCY
(2)
See figure 5.
SCK
64
×
μs
T
CYC
*
9
Input clock low-level pulse
width
t
CKL
(1)
See figure 5.
SCK
1.0
μs
Output clock low-level pulse
width
t
CKL
(2)
See figure 5.
SCK
32
×
T
CYC
μs
Input clock high-level pulse
width
t
CKH
(1)
See figure 5.
SCK
1.0
μs
Output clock high-level pulse
width
t
CKH
(2)
See figure 5.
SCK
32
×
T
CYC
μs
Serial input
Data setup time
t
ICK
Stipulated with respect to
the SCK rising edge.
SI
0.5
μs
Data hold time
t
CKI
See figure 5.
SI
0.5
μs
Serial output
Output delay time
t
CKO
Stipulated with respect to
the SCK falling edge.
With external 1 k
resistors and 50 pF
capacitors on the
n-channel open-drain
outputs only.
See figure 5
SO
0.5
μs
Pulse output
Period
t
PCY
PE0
64
×
T
CYC
32
×
T
CYC
±10%
32
×
T
CYC
±10%
μs
High-level pulse width
t
PH
PE0
μs
Low-level pulse width
t
PL
PE0
μs
See figure 6
T
CYC
= 4
×
<system clock
period>
With external 1 k
resistors and external
50 pF capacitors on the
n-channel open-drain
outputs only.
Notes: 1. Voltages up to the generated oscillation amplitude are allowed with internal drive using the oscillator circuit of figure 2 and the recommended circuit
constants.
2. The average over a 100 ms period.
3. Applications must hold the operating supply voltage V
DD
level from the point a HALT instruction is executed until the IC enters the standby state.
Also, switch bounce and similar noise must not appear on PA3 (or PA0 to 3) during the HALT instruction execution cycle.
4. The recommended circuit constants for which stable oscillation has been verified with the manufacturer of the oscillator element using the Sanyo
specified oscillator characteristics evaluation board.
5. The OSC1 pin has Schmitt trigger characteristics when external clock is specified as the oscillator option.
6. The result of measurement when the recommended external circuit constants are used with the Sanyo characteristics evaluation board. The current
due to the IC output transistors and pull-up resistor transistors is not included.
7. Indicates the frequency when f
CFOSC
is due to the use of the recommended circuit constants in table 1.
8. Indicates the required time for oscillation to stabilize starting from the point when V
DD
first exceeds the lower limit of the operating supply voltage
range. (See figure 3.)
9. T
CYC
= 4
×
<system clock period>
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| LC651431L | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Four-Bit CMOS Microcontrollers for Small-Scale Control Applications |
| LC651431N | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Four-Bit CMOS Microcontrollers for Small-Scale Control Applications |
| LC651432F | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Four-Bit CMOS Microcontrollers for Small-Scale Control Applications |
| LC651432L | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Four-Bit CMOS Microcontrollers for Small-Scale Control Applications |
| LC651432N | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Four-Bit CMOS Microcontrollers for Small-Scale Control Applications |
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