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參數(shù)資料
| 型號： | LC651154F |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Four-Bit CMOS Microcontrollers for Small-Scale Control Applications |
| 中文描述： | 4位CMOS微控制器的小規(guī)?？刂浦械膽?/td> |
| 文件頁數(shù)： | 31/39頁 |
| 文件大?。?/td> | 336K |
| 代理商： | LC651154F |
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Parameter
Symbol
Conditions
Applicable pins and notes
Ratings
Unit
min
typ
max
Oscillator characteristics
Figure 3, fo = 400 kHz
Figure 3, fo = 800 kHz
Figure 3, fo = 1 MHz
Figure 3, fo = 4 MHz, with the
divide-by-four
circuit used.
OSC1, OSC2
OSC1, OSC2
OSC1, OSC2
OSC1, OSC2
392
784
980
3920
400
800
1000
4000
408
816
1020
4080
Ceramic oscillator
Oscillator frequency
f
CFOSC
*
7
kHz
Figure 4, fo = 400 kHz
Figure 4, fo = 800 kHz, 1 MHz, or
4 MHz, with the divide-by-four
circuit used.
10
10
Oscillator stabilization time
*
8
t
CFS
ms
Two-pin RC oscillator
Oscillator frequency
f
MOSC
Figure 2, Cext = 270 pF ±5%
Figure 2, Rext = 5.6 k
±1%
Output n-channel transistors off
V
IN
= V
SS
, V
DD
= 5 V
V
IN
= V
SS
, V
DD
= 5 V
OSC1, OSC2
290
400
841
kHz
Pull-up resistor
I/O ports
RPP
Pull-up resistor
specification ports
8
14
30
k
RES
Ru
RES
200
500
800
External reset characteristics
Reset time
t
RST
See figure 5.
f = 1 MHz
With all pins other than the pin
being tested at V
IN
= V
SS
.
Pin capacitances
Cp
10
pF
Serial clock
Input clock cycle time
t
CKCY
(1)
Figure 6
SCK
2.0
Output clock cycle time
t
CKCY
(2)
Figure 6
SCK
64
×
T
CYC
*
9
Input clock low-level pulse
width
t
CKL
(1)
Figure 6
SCK
2.0
Output clock low-level pulse
width
t
CKL
(2)
Figure 6
SCK
32
×
T
CYC
Input clock high-level pulse
width
t
CKH
(1)
Figure 6
SCK
2.0
Output clock high-level
pulse width
t
CKH
(2)
Figure 6
SCK
32
×
T
CYC
Serial input
Data setup time
t
ICK
SI
0.5
μs
Data hold time
t
CKI
SI
0.5
Serial output
Stipulated with respect to the
falling edge of SCK.
With an external resistor of 1 k
and an external capacitor of 50 pF
on only the n-channel open-drain
pins.
Figure 6
SO
1.0
Output delay time
t
CKO
Pulse output function
Period
t
PCY
PE0
64
×
T
CYC
High-level pulse width
t
PH
PE0
32
×
T
±10%
Low-level pulse width
tPL
PE0
32
×
T
±10%
Stipulated with respect to the
rising edge of SCK.
Figure 6
No. 6278-31/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Continued on next page.
Figure 7
TCYC = 4
×
system clock
period
With an external resistor of
1 k
and an external
capacitor of 50 pF on only
the n-channel open-drain
pins.
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相關代理商/技術(shù)參數(shù) |
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|---|---|
| LC651154L | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Four-Bit CMOS Microcontrollers for Small-Scale Control Applications |
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| LC651202F(30DIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller |
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