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參數(shù)資料
| 型號： | LB1814M |
| 元件分類： | 運動控制電子 |
| 英文描述： | DISK DRIVE MOTOR CONTROLLER, 1 A, PDSO36 |
| 封裝： | 0.375 INCH, MFP-36 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 162K |
| 代理商： | LB1814M |
LB1814M
No.5198-3/13
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
FG amplifier block
Input offset voltage
VIO(FG)
-10
+10
mV
Input bias current
IB(FG)
-1
+1
A
DC bias level
VB(FG)
1.8
1.9
2.0
V
Output high level voltage
VOH(FG)
IFGI= -100A, No external load
2.3
2.7
3.1
V
Output low level voltage
VOL(FG)
IFGI=100A, No external load
0.8
1.2
1.6
V
FG Schmitt block
Input hysteresis (high to low)
VSHL
0
mV
Input hysteresis (low to high)
VSLH
140
mV
Hysteresis width
VFGL
90
200
mV
Input operating level
VFGSIL
400
mVp-p
Error amplifier block
Input offset voltage
VIO(ER)
Design target value
-10
+10
mV
Input bias current
IB(ER)
-1
+1
A
DC bias level
VB(ER)
-5%
1/2VREG
+5%
V
VOH(ER)1
No external load
VREG-1.0
V
Output high level voltage
VOH(ER)2
ILOAD=2mA
VREG-1.5
V
Output low level voltage
VOL(ER)
No external load
1.0
V
Phase comparator output
Output high level voltage
VPDH
No external load
VREG-0.2
V
Output low level voltage
VPDL
No external load
0.1
0.2
V
Output source current
IPD+
VPD=VREG / 2
-0.4
mA
Output sink current
IPD-
VPD=VREG / 2
2.5
mA
Lock detector output
Output saturation voltage
VLDSAT
ILD=1.5mA
0.1
0.4
V
Output leakage current
ILDLEAK
VLD=13.5V
10
A
Rotation monitor output
Output saturation voltage
VHGSAT
IHG=1.5mA
0.1
0.4
V
Output leakage current
IHGLEAK
VHG=13.5V
10
A
Stop sensor output
Output saturation voltage
VSDSAT
ISD=1.5mA
0.1
0.4
V
Output leakage current
ISDLEAK
VSD=13.5V
10
A
Drive block
Dead zone width
VDZ
50
195
300
mV
Output idling voltage
VID
6mV
Forward gain
GDF+
0.4
0.5
0.6
Reverse gain
GDF-
-0.6
-0.5
-0.4
Forward limiter voltage
VL+
Rf=10, VEI=0V
0.21
0.23
0.25
V
Reverse limiter voltage
VL-
Rf=10, VEI=VREG
0.16
0.18
0.20
V
Reference signal block
Crystal oscillator frequency
fOSC
In crystal oscillator mode
1
10
MHz
Hall bias pin
Sink current
IHB
10
mA
Analog filter block
Delay time 1
TFD1
Rising
5.0
9.0
13.5
s
Delay time 2
TFD2
Falling
4.5
8.5
13.0
s
S/B pin
High level input voltage
VSBH
VCC-1.5
VCC
V
Low level input voltage
VSBL
0
VCC-3.5
V
Input open voltage
VSBO
VCC-0.2
VCC
V
Low level input current
ISBL
VSB=0V
-200
-140
-80
A
Continued on next page.
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