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參數(shù)資料
| 型號： | LB1814M |
| 元件分類： | 運動控制電子 |
| 英文描述： | DISK DRIVE MOTOR CONTROLLER, 1 A, PDSO36 |
| 封裝： | 0.375 INCH, MFP-36 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 162K |
| 代理商： | LB1814M |
LB1814M
No.5198-11/13
External Components and Description
Components
Function
Description
C1
Power stabilization
Selects a value at which voltage fluctuations, due to
motor driving current, are stabilized.
C2
Internal circuit power stabilization
Stabilizes voltage fluctuations in the 3.8V regulator
output.
C3
Control amplifier frequency characteristics correction
Stops oscillation in the closed loop of the current
control system.
R1
Current limiting
Limits output current according to the equation
IOUT=VRF1/R1.
C4, C5, C6
Suppresses output oscillation.
C7
Brake control
Controls motor stop characteristics by adjusting the
capacitance of this capacitor.
C8, C9, C10
Improves noise immunity of the Hall signal.
C11
AGC amplifier frequency characteristics correction.
Initial reset pulse generation.
Smoothes out ripples.
Generates an initialization reset to the IC's internal
logic.
C12, C13
External crystal oscillator components
R2, R3, C14, C15
FG amplifier gain and frequency characteristics setting
R4, R5, R6, R7, C16, C17, C18
Servo constant
R8, R9, R10
Pull-up resistors
LB1814M Functional Description and External Components
1. Speed control circuit
This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter.
This PLL circuit compares the phase at the falling edge of the reference clock signal and falling edge of the FG pulse,
and outputs the phase error. The FG servo frequency is determined by the following formula, so the motor speed
must be determined by the number of FG pulses and crystal oscillator frequency.
fFG (servo) = Crystal oscillator frequency/Clock divisor
2. Three-phase full-wave current linear drive
This IC adopts a three-phase full-wave current linear drive to hold motor noise to an absolute minimum.
It suppresses motor noise by smoothing the output current waveform. Since oscillation may occur in the output block
depending on the motor used, the capacitors C4, C5 and C6 (of approx. 0.1
F) are connected between the OUT pins
and ground.
3. Current limiting circuit
The current limiting circuit limits the current (i.e., the peak current) to the level determined by the formula
IOUT=VRF1/R1. In the reverse torque mode (braking), the current is limited to the level determined by the formula
IOUT=VRF2/R1. A scheme in which the output drive current is limited is adopted for limiting operation. This
necessitates the phase compensation capacitor C3 (of approx. 0.1
F) connected between the FC pin and ground.
4. FG amplifier
The gain of the FG amplifier is determined by R2 and R3. G = R3/R2 defines the DC gain. C14 and C15 determine
the frequency characteristics of the FG amplifier (R2 and C14 make up a high-pass filter and R3 and C15 a low-pass
filter).
Since a Schmitt comparator follows the FG amplifier, it is necessary to determine the values of R2, R3 and C14, C15
so that the FG amplifier output is always 400mVp-p or higher. (It is desirable for the FG amplifier output to be set up
to be between 1 and 3Vp-p during steady state rotation.) If the noise immunity level poses problems in noise
evaluation, connect a capacitor of between 1000pF to 0.1F between FGOUT pin and ground.
The FGIN- pin also serves to switch the Hall FG mode and pattern FG mode. When the Hall FG mode is selected, the
pin must be connected to the VREG pin.
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