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參數(shù)資料
| 型號： | LAMXO640E-3TN144E |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 7/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 640LUTS 144TQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | LA-MachXO |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 4.9ns |
| 電壓電源 - 內(nèi)部： | 1.14 V ~ 1.26 V |
| 宏單元數(shù)： | 320 |
| 輸入/輸出數(shù)： | 113 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
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2-12
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
The EBR memory supports three forms of write behavior for single or dual port operation:
1.
Normal – data on the output appears only during the read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2.
Write Through – a copy of the input data appears at the output of the same port. This mode is supported for all
data widths.
3.
Read-Before-Write – when new data is being written, the old contents of the address appears at the output.
This mode is supported for x9, x18 and x36 data widths.
FIFO Conguration
The FIFO has a write port with Data-in, CEW, WE and CLKW signals. There is a separate read port with Data-out,
RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The
Full and Almost Full ags are registered with CLKW. The Empty and Almost Empty ags are registered with CLKR.
The range of programming values for these ags are in Table 2-7.
Table 2-7. Programmable FIFO Flag Ranges
The FIFO state machine supports two types of reset signals: RSTA and RSTB. The RSTA signal is a global reset
that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO ags in their initial reset
state. The RSTB signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in
the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the
FIFO.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respec-
tively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both
ports are as shown in Figure 2-13.
Flag Name
Programming Range
Full (FF)
1 to (up to 2
N-1)
Almost Full (AF)
1 to Full-1
Almost Empty (AE)
1 to Full-1
Empty (EF)
0
N = Address bit width
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| LAMXO640LUTSE-3FTN256E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LA-MachXO Automotive Family Data Sheet |
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