參數(shù)資料
型號: LAMXO256E-3TN100E
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 39/77頁
文件大?。?/td> 0K
描述: IC FPGA AUTO 256LUTS 100-TQFP
標準包裝: 90
系列: LA-MachXO
可編程類型: 系統(tǒng)內可編程
最大延遲時間 tpd(1): 4.9ns
電壓電源 - 內部: 1.14 V ~ 1.26 V
宏單元數(shù): 128
輸入/輸出數(shù): 78
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-TQFP(14x14)
包裝: 托盤
其它名稱: 220-1638
LAMXO256E-3TN100E-ND
3-18
DC and Switching Characteristics
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
Switching Test Conditions
Figure 3-6 shows the output test load that is used for AC testing. The specic values for resistance, capacitance,
voltage, and other test conditions are shown in Figure 3-5.
Figure 3-6. Output Test Load, LVTTL and LVCMOS Standards
Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
R1
CL
Timing Ref.
VT
LVTTL and LVCMOS settings (L -> H, H -> L)
0pF
LVTTL, LVCMOS 3.3 = 1.5V
LVCMOS 2.5 = VCCIO/2
LVCMOS 1.8 = VCCIO/2
LVCMOS 1.5 = VCCIO/2
LVCMOS 1.2 = VCCIO/2
LVTTL and LVCMOS 3.3 (Z -> H)
188
0pF
1.5
VOL
LVTTL and LVCMOS 3.3 (Z -> L)
VOH
Other LVCMOS (Z -> H)
VCCIO/2
VOL
Other LVCMOS (Z -> L)
VCCIO/2
VOH
LVTTL + LVCMOS (H -> Z)
VOH - 0.15
VOL
LVTTL + LVCMOS (L -> Z)
VOL - 0.15
VOH
Note: Output test conditions for all other interfaces are determined by the respective standards.
DUT
VT
R1
CL
Test Poi nt
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