參數(shù)資料
型號: LAMXO256E-3TN100E
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 23/77頁
文件大?。?/td> 0K
描述: IC FPGA AUTO 256LUTS 100-TQFP
標(biāo)準(zhǔn)包裝: 90
系列: LA-MachXO
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 4.9ns
電壓電源 - 內(nèi)部: 1.14 V ~ 1.26 V
宏單元數(shù): 128
輸入/輸出數(shù): 78
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
其它名稱: 220-1638
LAMXO256E-3TN100E-ND
Introduction
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
1-2
high-security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and
careful design will provide the high pin-to-pin performance also associated with CPLDs.
The ispLEVER
design tools from Lattice allow complex designs to be efciently implemented using the LA-
MachXO automotive family of devices. Popular logic synthesis tools provide synthesis library support for LA-
MachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its oor planning tools
to place and route the design in the LA-MachXO device. The ispLEVER tool extracts the timing from the routing
and back-annotates it into the design for timing verication.
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