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參數(shù)資料
| 型號： | LA7578N |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | IF Signal Processing (Super PLL-II VIF + SIF) Circuit for TVs and VCRs(用于電視機/VCR應用的IF信號處理（超鎖相環(huán)II VIF+SIF）電路) |
| 中文描述： | 中頻信號處理（超鎖相環(huán)-Ⅱ資料表格應力強度因子）的電視和錄像機電路（用于電視機/錄像機應用的中頻信號處理（超鎖相環(huán)二資料表格強度因子）電路） |
| 文件頁數(shù)： | 15/18頁 |
| 文件大小： | 237K |
| 代理商： | LA7578N |
Series resonance
Fig. 24
Fig. 25
Pins 19, 20, and 21 (EQ amplifier)
These pins are for the equalizer amplifier. A signal that has
passed through a 4.5 MHz trap is input to pin 19 and is output
from pin 21. Pin 21 is of emitter follower. A resistor must be
connected between pin 21 and GND in order to attain
satisfactory drive capability.
V
CC
= 12 V
V
CC
= 9 V
In addition, in order to draw the signal out externally, an
external buffer transistor is required.
R
^
2.7 k
R
^
2.2 k
(1) Equalizer amplifier design
The equalizer amplifier consists of a voltage follower with
a voltage gain of 0 dB. To compensate for the frequency
characteristics, externally connect L, C, and R as shown in
Fig. 26. Operation in this case is as follows:
Assigning the input to vi and the output to vo,
(R1/Z + 1) (vi + vin) = vo
Assuming imaginary short state,
if vin
6
0, then:
Av = vo/vi = R1/Z + 1
If the application of pin 20 is as shown in Fig. 27, it can be
used as a voltage amplifier.
One point that requires caution, however, is the dynamic range
of the equalizer amplifier. In short, the bleeder resistance ratio
must be designed so that signals are not amplified excessively,
and so that the leading edge voltage of the video signal sync
signal is not too high or too low. In other words, the design
must be such that the sync signal voltage does not change.
LA7578N
No.4952-15/18
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LA7583 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:IF Signal Processing Circuit (A2C PLL VIF + SIF) for TVs and VCRs |
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