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參數(shù)資料
| 型號： | LA6513A |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 332K |
| 代理商： | LA6513A |
LC6512A, LC6513A
No.2367–7/24
τ
V
DD
: Power supply rise time constant
τ
RES
: RES pin rise time constant
Fix C. R so that
τ
V
DD
τ
RES
, t
OSC
>
tOSC
: OSC stabilized time
KBR3.0MS (Kyocera)
22
±
10%
33
±
10%
C1 (pF)
C2 (pF)
CSB400P (Murata)
KBR800H (Kyocera)
Ceramic resonator
CSB800K, D (Murata)
KBR1000H (Kyocera)
CSB1000K, D (Murata)
CSA3.00MG (Murata)
1MHz
330
±
10%
180
±
10%
180
±
10%
180
±
10%
180
±
10%
Center frequency
800kHz
3MHz
330
±
10%
400kHz
KBR400B (Kyocera)
Note 2) There is a tolerance of approximately 1% between the center frequency at the ceramic resonator mode and the
nominal value presented by the ceramic resonator supplier. For details, refer to the specification for the ceramic
resonator.
The min., max. values of OSC frequency represent the oscillatable frequency range.
Note 3) When using the piggyback microcomputer, evaluation chip for evaluation, connect a feedback resistor (approxi-
mately lM
).
Fig. 2 Recommended OSC circuit, constants
for ceramic resonator OSC
CF: Ceramic resonator
CSA3.00MG (Murata)
KBR3.0MS (Kyocera)
CSB1000K, D (Murata)
KBR1000H (Kyocera)
CSB800K, D (Murata)
KBR800H (Kyocera)
CSB400P (Murata)
KBR400B (Kyocera)
Input/output common ports C, D: Output inhibit
HALT instruction is executed to provide HALT mode.
Fig. 3 I
DD
(2) test circuit
Fig. 4 I
DD
(3) test circuit
Fig. 5 lnitial reset timing
<
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