參數(shù)資料
型號: LA4032V-75TN44E
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 16/42頁
文件大小: 0K
描述: IC CPLD 32MACROCELLS 44TQFP
標(biāo)準(zhǔn)包裝: 160
系列: LA-ispMACH
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
宏單元數(shù): 32
輸入/輸出數(shù): 30
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
23
LA-ispMACH 4000V/Z Timing Adders
1
Adder Type
Base Parameter
Description
LA-ispMACH 4000V
-75
LA-ispMACH 4000Z
-75
Units
Min.
Max.
Min.
Max.
Optional Delay Adders
tINDIO
tINREG
Input register delay
1.00
1.30
ns
tEXP
tMCELL
Product term expander delay
0.33
0.50
ns
tORP
Output routing pool delay
0.05
0.40
ns
tBLA
tROUTE
Additional block loading adder
0.05
0.05
ns
tIOI Input Adjusters
LVTTL_in
tIN, tGCLK_IN, tGOE Using LVTTL standard
0.60
0.60
ns
LVCMOS33_in
tIN, tGCLK_IN, tGOE Using LVCMOS 3.3 standard
0.60
0.60
ns
LVCMOS25_in
tIN, tGCLK_IN, tGOE Using LVCMOS 2.5 standard
0.60
0.60
ns
LVCMOS18_in
tIN, tGCLK_IN, tGOE Using LVCMOS 1.8 standard
0.00
0.00
ns
PCI_in
tIN, tGCLK_IN, tGOE Using PCI compatible input
0.60
0.60
ns
tIOO Output Adjusters
LVTTL_out
tBUF, tEN, tDIS
Output congured as TTL buffer
0.20
0.20
ns
LVCMOS33_out tBUF, tEN, tDIS
Output congured as 3.3V buffer
0.20
0.20
ns
LVCMOS25_out tBUF, tEN, tDIS
Output congured as 2.5V buffer
0.10
0.10
ns
LVCMOS18_out tBUF, tEN, tDIS
Output congured as 1.8V buffer
0.00
0.00
ns
PCI_out
tBUF, tEN, tDIS
Output congured as PCI
compatible buffer
0.20
0.20
ns
Slow Slew
tBUF, tEN
Output congured for slow slew
rate
1.00
1.00
ns
Note: Open drain timing is the same as corresponding LVCMOS timing.
Timing v.3.2
1. Refer to TN1004, ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
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