參數(shù)資料
型號(hào): LA4032V-75TN44E
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 13/42頁(yè)
文件大?。?/td> 0K
描述: IC CPLD 32MACROCELLS 44TQFP
標(biāo)準(zhǔn)包裝: 160
系列: LA-ispMACH
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
宏單元數(shù): 32
輸入/輸出數(shù): 30
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤(pán)
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
20
Timing Model
The task of determining the timing through the LA-ispMACH 4000V/Z automotive family, like any CPLD, is relatively
simple. The timing model provided in Figure 11 shows the specic delay paths. Once the implementation of a given
function is determined either conceptually or from the software report le, the delay path of the function can easily
be determined from the timing model. The Lattice design tools report the timing delays based on the same timing
model for a particular design. Note that the internal timing parameters are given for reference only, and are not
tested. The external timing parameters are tested and guaranteed for every device. For more information on the
timing model and usage, refer to TN1004, ispMACH 4000 Timing Model Design and Usage Guidelines.
Figure 11. LA-ispMACH 4000V/Z Automotive Timing Model
DATA
MC Reg.
C.E.
S/R
Q
SCLK
IN
OE
In/Out
Delays
In/Out
Delays
Control
Delays
Register/Latch
Delays
Routing/GLB Delays
Out
Note: Italicized items are optional delay adders.
tFBK
Feedback
From
Feedback
tBUF
tPDb
tMCELL
tPTCLK
tBCLK
tPTSR
tBSR
tGPTOE
tPTOE
tEXP
tROUTE
tBLA
tINREG
tINDIO
tIN
tIOI
tGCLK_IN
tIOI
tGOE
tIOI
tPDi
tIOO
tORP
tEN
tDIS
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