參數(shù)資料
型號(hào)： L9952GXP
廠商： STMICROELECTRONICS
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO36
封裝： LEAD FREE, SSO-36
文件頁數(shù)： 44/68頁
文件大?。?/td> 859K
代理商： L9952GXP
L9952GXP
Electrical characteristics
Doc ID 13518 Rev 5
7.14.3
Input PWM 2 Vth for flash mode
The voltages are referred to ground.
6V < VS < 18V; 4.5V < V1 < 5.3V; all outputs open; Tj = -40°C...130°C, unless otherwise
specified.
7.14.4
DI timing
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V < VS < 18V; 4.5V < V1 < 5.3V; all outputs open; Tj = -40°C...130°C,
unless otherwise specified.
Table 30.
Input PWM2 Vth for flash mode
Item
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
7.14.13
Vin L
Input low level (Vin rising))
V1 = 5 V
6.1
7.25
8.4
V
7.14.14
Vin H
Input high level
(Vin falling)
V1 = 5 V
7.4
8.4
9.4
V
7.14.15
Vin Hyst
Input hysteresis
V1 = 5 V
0.6
0.8
1.0
V
Table 31.
DI timing
Item
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
7.14.16
tCLK
Clock period
V1 = 5 V
1000
-
ns
7.14.17
tCLKH
Clock high time
V1 = 5 V
400
-
ns
7.14.18
tCLKL
Clock low time
V1 = 5 V
400
-
ns
7.14.19
tset CSN
CSN setup time, CSN low
before rising edge of CLK
V1 = 5 V
400
-
ns
7.14.20
tset CLK
CLK setup time, CLK high
before rising edge of CSN
V1 = 5 V
400
-
ns
7.14.21
tset DI
DI setup time
V1 = 5 V
200
-
ns
7.14.22
thold DI
DI hold time
V1 = 5 V
200
-
ns
7.14.23
tr_in
Rise time of input signal
DI, CLK, CSN
V1 = 5 V
-
100
ns
7.14.24
tf_in
Fall time of input signal
DI, CLK, CSN
V1 = 5 V
-
100
ns
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