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參數(shù)資料
| 型號(hào)： | L9949 |
| 廠(chǎng)商： | 意法半導(dǎo)體 |
| 英文描述： | DOOR ACTUATOR DRIVER |
| 中文描述： | 門(mén)執(zhí)行器驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 16/20頁(yè) |
| 文件大小： | 334K |
| 代理商： | L9949 |
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L9949
16/20
Figure 8. SPI-Interface - Transfer Timing Diagram
I
DOLK
Tristate Leakage Current
V
CSN
= V
CC
, 0 V < V
DO
< V
CC
-10
10
μ
A
C
DO
Tristate Input Capacitance
V
CSN
= V
CC
,
0 V < V
CC
< 5.5 V
10
15
pF
DO timing (see Figg. 10 & 11)
t
r DO
DO Rise Time
C
L
= 100 pF, I
load
= -1mA
50
100
ns
t
f DO
Data Out Fall Time
C
L
= 100 pF, I
load
= 1mA
50
100
ns
t
en DO tri L
DO Enable Time
from tristate to low level
C
L
= 100 pF, I
load
= 1mA
pull-up load to V
CC
80
250
ns
t
en DO L tri
DO Disable Time
from low level totristate
C
L
= 100 pF, I
load
= 4mA
pull-up load to V
CC
200
400
ns
t
en DO tri H
DO Enable Time
from tristate to high level
C
L
= 100 pF, I
load
= -1mA
pull-down load to GND
80
250
ns
t
en DO H tri
DO Disable Time
from high level totristate
C
L
= 100 pF, I
load
= -4mA
ppull-down load to GND
200
400
ns
t
d DO
DO Delay Time
V
DO
< 0.3 V
CC
, V
DO
> 0.7 V
CC
,
C
L
= 100 pF
50
250
ns
(1)
(2)
Value of input capacity is not measured in production test. Parameter guarenteed by design.
DI timing parameters tested in production by a passed/failed test:
Tj=-40°C/+25°C: SPI communication @2MHz
Tj=+125°C:
SPI communication @1.25MHz
SPI INTERFACE ELECTRICAL CHARACTERISTCS
(continued)
V
S
= 8 to 16 V, V
CC
= 4.5 to 5.5 V, T
j
= -40 to 150 °C, unless otherwise specified. The voltages are refered to
GND and currents are assumed positive, when the current flows into the pin
.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
0
1
0
1
time
time
time
time
time
CSN high to low: DO enabled
actual data
DI: data will be accepted on the rising edge of CLK signal
new data
CSN
CLK
DI
DO
e.g.OUT1
DO: data will change on the falling edge of CLK signal
status information
6
7
fault bit
CSN low to high: actual data is
transfered to output power switches
old data
1
2
3
4
5
6
7
8
9
10
11
0
12
13
14 15
1
0
actual
l
data
1
2
3
4
5
6
7
8
9
10 11
0
12
13 14 15
1
2
3
4
5
8
9
10 11
0
12
13 14 15
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