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參數(shù)資料
| 型號： | L9929XP |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SPI CONTROLLED H-BRIDGE |
| 中文描述： | 可控的SPI H橋 |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 629K |
| 代理商： | L9929XP |
9/23
L9929
3
Truth Table
Table 7. Truth Table
t
dt
Transfer Delay (8)
(referred to master)
Serial clock high time (9)
(referred to master)
Access time (10)
(referred to master)
Clock inactive before
chipselect becomes valid (11)
Clock inactive after
chipselect becomes valid (12)
Rise-, fall time
150
ns
t
SCKH
50
ns
t
SCKL
8.35
μ
s
200
ns
200
ns
t
rs
Load on SO 50pF
20
ns
TIMING
Diagnostic Threshold
(Open Load Detection DMS > 3.1V, EN < 18V and/or DI > 2V)
Load is available
V
OUT1
V
OUT2
V
OUT1
V
OUT2
I
OUT2
I
OUT1
0.8
0.8
V
V
Load is missing
1
V
S
0.8
V
V
Diagnostic Current
DMS > 3.1V, EN < 0.8V
EN < 18V and/or DI > 2V
700
1000
1000
1500
1350
2000
μ
A
μ
A
Tracking Diagnostic Current
I
OUT1
/ I
OUT2
* After disabling the device, the
load has to be demagnetized
during tD ,to avoid erroneous OL
detection
1.4
1.5
1.6
t
D
Delay Time
30
100
ms
Pos.
DI
EN
IN1
IN2
OUT1
OUT2
SF
3)
SPI
4)
DIA_REG
1. Forward
2. Reverse
3. Free-wheeling low
4. Free-wheeling high
5. Disable
6. Enable
7. IN1 disconnected
8. IN2 disconnected
9. DI disconnected
10. EN disconnected
11. Current limit. active
12. Undervoltage active
1.)
13. Overtemperature
2.)
14. Overcurrent
2.)
L
L
L
L
H
X
L
L
Z
X
L
X
H
H
H
H
X
L
H
H
X
Z
H
X
H
L
L
H
X
X
Z
X
X
X
X
X
L
H
L
H
X
X
X
Z
X
X
X
X
H
L
L
H
Z
Z
H
X
Z
Z
Z
Z
L
H
L
H
Z
Z
X
H
Z
Z
Z
Z
H
H
H
H
L
Z
H
L
L
L
H
L
See
Diagnostics
/ Encoding
of Failures
X
X
X
X
Z
Z
L
X
X
X
X
Z
Z
L
Table 5. Electrical Characteristcs
(continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
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