參數(shù)資料
型號(hào)： L9929XP
廠商： 意法半導(dǎo)體
英文描述： SPI CONTROLLED H-BRIDGE
中文描述： 可控的SPI H橋
文件頁(yè)數(shù)： 13/23頁(yè)
文件大小： 629K
代理商： L9929XP
13/23
L9929
6)
7)
On the read access the databits at the SPI input SI are rejected.
Invalid instruction/access: An instruction is invalid, if one of the following conditions is fulfilled:
– An unused instruction code is detected (see tables with SPI instructions).
– In case the previous transmission is not completed in terms of internal data processing. ( Violation of
the minimum Access-Time. )
– In case of the previous transmission has detected more than 16 SCK pulses
– Reset has occurred (Undervoltage on DMS)
If an invalid instruction is detected, any modifications on registers of L9929 are not allowed.
In case an unused instruction code occured the databyte "ffh ex" will be transmitted after having sent the check
byte.
In addition any access is invalid if the number of SPI clock pulses (falling edge) counted during active SS differs
from exactly 16 clock pulses (-> See Note).
5.4
SPI Communication
Figure 13. Reading access / 8 bit
5.5
The uppermost 2 bit of the instruction byte contains the chipadress. The chipaddress of L9929 is 00.
SPI Instruction
MSB
7
0
6
0
5
4
3
2
1
0
INSTR5
INSTR4
INSTR3
INSTR2
INSR1
INSR0
SPI Instruction
Encoding
bit 5,4,3,2,1,0
INSTR(5...0)
000 000
000 011
Description
bit 7,6
CPAD1,0
00
00
RD_IDENT
RD_VERSION
Read identifier
Read version
RD_DIA
00
001 001
All others
Read DIA_REG
No function
SPI INSTRUCTION
MSB
XXXX XXXX
SS
SI
VERIFICATION BYTE
MSB
DATA/8 BIT
MSB
SO
D01AT480
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