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參數(shù)資料
| 型號(hào)： | L9903 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | MOTOR BRIDGE CONTROLLER |
| 中文描述： | 汽車橋控制器 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大小： | 131K |
| 代理商： | L9903 |
15/17
L9903
FUNCTIONAL DESCRIPTION (continued)
Programmable cross conductionprotection
The external power MOS transistors in H-Bridge ( two half bridges) configuration are switched on with an addi-
tional delay time t
CCP
to prevent cross conduction in the halfbridge. The cross conduction protection time
t
CCP
isdetermined by the external capacitor C
PR
and resistor R
PR
at the PR pin. The capacitor C
PR
is charged
up to the voltage limit V
PRH
. A level change on the control inputs DIR and PWM switches off the concerned ex-
ternal MOS transistor and the charging source at the PR pin. The resistor R
PR
discharges the capacitor C
PR
.
The concerned external power MOS transistor will be switched on again when the voltage at PR reaches the
value of V
PRL
. After that the CPR will be charged again. The capacitor C
PR
should be choosen between 100pF
and 1nF. The resistor R
PR
should be higher than 7kW. The delay time can be expressed as follows:
t
CCP
= R
PR
· C
PR
· ln N
PR
with N
PR
= V
PRH
/ V
PRL
= 2
t
CCP
= 0.69 · R
PR
· C
PR
ISO-Interface
The ISO-Interface provides the communication between the micro controller and a serial bus with a baud rate
up to 60kbit/s via a single wire which is V
BAT
and GND compatible. The logic level transmission input TX drives
the open drain K-output. The K output can be connected to a serial bus with a pull up resistor to V
BAT
. The K-
pin is protected against overvoltage, short to GND and VSand canbe driven beyond V
VS
and GND. During lack
of V
VS
or GND the output shows high impedance characteristic. The open drain output RX with an internal pull
up resistor monitors the status at the K-pin to read the received data and control the transmitted data. Short
circuit condition at K-pin is recognized if the internal open drain transistor isn’t able to pull the voltage potential
at K-pin below the threshold of 0.45·V
VS
. Then the RX stays in high condition. A timer starts and switches the
open drain transistor after typ. 20
μ
s off. A next low at the TX input resets the timer and the open drain transistor
switches on again.
Figure 8. Functional schematic of the ISO-interface
RX
TX
K
VCC
RRX
0.5
VVS
TX
R
TSH
delay
=
R
S
Q
R
I
KH
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