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L9848
–
Initial Fault Register SPI Cycle
After initial application of VDD to the L9848, the fault register is "Cleared" by the POR circuitry during
the initial SPI cycle, and all subsequent cycles, valid fault data will be clocked out of DO (fault bits).
The bits that are "Set" indicate which particular output(s) have a fault condition.
– Incandescent Lamp Outputs
Software filtering may be needed to ignore fault signals due to the long turn on delay associated with
lamp loads. For example, the lamp load channel gets enabled during one SPI cycle. Approximately
20ms-100ms later, a SPI cycle is required to read the correct fault latch data, which will be cleared
after the falling edge of CS of that SPI cycle.
Configuration for Output1-6
The drain and source pins for each output must be connected in one of the two following configurations (see
Figure 6a and Figure 6b).
–
Low Side Drivers
When any combination of Output1-6 are connected in a low side drive configuration the source of the
applicable output (SRC1-6) has to be connected to ground. The drain of the applicable output (DRN1-
6) has to be connected to the low side of the load.
–
High Side Drivers
When any combination of Output1-6 are connected in a high side drive configuration the drain of the
applicable output (DRN1-6) has to be connected to VBatt. The source of the applicable output
(SRC1-6) has to be connected to the high side of the load.
DRN1-6 Susceptibility to Negative Voltage Transients
For any output(s) connected and used for a high side drive a fast negative transient slew rate does not inadvert-
ently issue a POR (power on reset) or cause parasitic latching to occur. Nevertheless under some conditions it
may be necessary to have a ceramic chip capacitor of 10nF to 100nF connected from drain to GND to aid in
preventing the occurance of a problem due to very fast negative transient(s) on the drain(s) of the device.
Thermal Shutdown
Each of the 8 outputs have independent thermal protection circuitry that disables each output driver once the
local n-channel MOSFET device temperature reaches the overtemperature shutdown limit. Due to the hystere-
sis of the enable and disable temperature levels the faulted channel will periodically turn off and on until the fault
condition is cleared, the ambient temperature is decreased sufficiently or the output is commanded OFF.
Once any individual channel goes into thermal shutdown, a logic "1" is latched into the Fault Register if it meets
the thermal fault filter (Note: does NOT go through the open/short fault filter).
Note:
Due to the design of the L9848 each output's thermal limit "may not" be truly independent to the extent that if one output is shorted,
it may impact the operation of other outputs (due to lateral heating in the die). The user may be required to monitor the fault bits
periodically. If a fault bit is "Set" for the last enabled output, and subsequently, fault bits for other enabled outputs start to be "Set",
the user will send two SPI write cycles within 100ms of each other. The first SPI write cycle will "Clear" the fault latches. If multiple
faults are indicated after the second SPI write cycle, these faults are most likely thermal faults. The user will then disable this output
that was most recently enabled. The fault register should be subsequently interrogated to verify proper operations of the other en-
abled output channels.
Charge Pump Usage
The L9848 uses a separate charge pump and oscillator for each of the 6 configurable output channels to provide
low RDSON values when connected in a high side configuration These oscillators are operating in a non-syn-
chronous mode of operation. The frequency range of these charge pumps is designed to be above the AM radio