參數(shù)資料
型號: L9848
廠商: 意法半導(dǎo)體
英文描述: OCTAL CONFIGURABLE LOW/HIGH SIDE DRIVER
中文描述: 八路可配置低/高邊驅(qū)動器
文件頁數(shù): 10/18頁
文件大小: 207K
代理商: L9848
L9848
10/18
the fault data bits out on the DO pin. CS has an integrated glitch filter for spurious pulses of 50ns or
shorter (i.e. no fault data and Outputs1-8 enable status will be altered). For open circuit condition the
CS is internally pulled down to GND.
Serial Clock (SCLK)
This is the clock signal input for synchronization of serial data transfer. DI data is shifted into the DI
input on the rising edge of SCLK and DO data changes on the falling edge of SCLK.
SPI DI Input Command Register
An input byte (8bits) is routed to the Command Register. The content of this Command Register is given in Table
1 and Table 2. Additional DI data will continue to be wrapped around to the DO pin. If CS will go low before a
complete reception of the current byte, this just transmitted byte will be ignored
Table 1. Bit Command Register Definition
Table 2. Command Register Logic Definition
Fault Operation
The fault diagnostic capability consists of one internal 8bit shift register. Open or shorted load detection is pro-
vided by comparing the source or drain voltage with the VDD voltage. When an output connected as either a
low side device or a high side device is commanded OFF, an open load can be detected. When an output con-
nected as either a low side device or a high side device is commanded ON a shorted load can be detected. The
fault bit is "set" for each channel if a short, open, or over-temperature condition occurs for Outputs1-8. The con-
tent of this Fault Register is given in Table 3. The output load status of each individual channel is defined in
Table 4. Open and shorts are subsequently re-latched provided they meet the minimum duration criterion and
thermal faults will be re-latched provided they meet the duration criterion after CS goes "LOW", if these fault
conditions are still present. The fault register is capable of detecting and latching multiple fault conditions
(among the 8 outputs) that have occurred between clearing of the fault flags.
All of the faults will be cleared on the falling edge of Chip Select (CS).
Table 3. Fault Register Definition
Table 4. Fault Logic Definition
MSB
LSB
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
D07
D06
D05
D04
D03
D02
D01
D00
BIT
STATE
STATUS
D00-D07
0
OUTPUT1-8 are commanded OFF
D00-D07
1
OUTPUT1-8 are commanded ON
MSB
LSB
Fault8
Fault7
Fault6
Fault5
Fault4
Fault3
Fault2
Fault1
D07
D06
D05
D04
D03
D02
D01
D00
BIT
STATE
STATUS
Fault1-8
0
OUT1-8 are not open or shorted (nominal)
Fault1-8
1
OUT1-8 are either open or shorted or in thermal shutdown
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