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參數(shù)資料
| 型號： | L9822ED |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CAP CER 1000PF 1KVDC B RAD |
| 中文描述： | 八路串行電磁驅(qū)動 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 112K |
| 代理商： | L9822ED |
TheL9822ESPDMOSoutputis a lowoperatingpo-
werdevicefeatu-ring,eight 1
R
DSON
DMOSdrivers
with transient protection circuits in output stages.
Eachchannelis independentlycontrolledbyan out-
putlatchanda commonRESETlinewhichdisables
all eight outputs.The driver has low saturationand
shortcircuitprotectionandcandriveinductiveandre-
sistive loads such as solenoids, lamps and relais.
DataistransmittedtothedeviceseriallyusingtheSe-
rialPeripheralInterface(SPI)protocol.Thecircuitre-
ceives 8 bit serial data by means of the serial input
(SI) which is stored in an internal register to control
theoutputdrivers.Theserialoutput(SO)provides8
bit of diagnosticdata representingthe voltage level
at the driver output.This allows the microprocessor
to diagnosethe conditionof theoutputdrivers.
The output saturation voltage is monitored by a
comparatorfor an outof saturationconditionandis
abletounlatchtheparticulardriverthroughthefault
resetline. This circuit is also cascadablewith ano-
ther octal driver in order to jam 8 bit multiple data.
The device is selected when the chip enable (CE)
lineis low.
Additionally the (SO) is placed in a tri-state mode
when the deviceis deselected.The negativeedge
of the(CE) transfersthe voltagelevel of thedrivers
totheshiftregisterandthepositiveedgeof the(CE)
latchesthenewdatafromtheshiftregistertothedri-
vers. When CE is Low, data bit contained into the
shift register is transferred to SO output at every
SCLKpositivetransitionwhile databitpresentatSI
inputislatchedintotheshiftregisteron everySCLK
negativetransition.
InternalBlocksDescription
The internal architectureof the deviceis based on
the threeinternalmajorblocks: the octalshiftregi-
sterfortalkingtothe SPIbus,theoctallatchforhol-
dingcontrolbitswrittenintothedeviceandthe octal
load driver array.
Shift Register
The shiftregisterhas bothserial andparallelinputs
and serial and parallel outputs.The serial inputac-
ceptsdatafromthe SPIbusandtheserial outputsi-
multaneously sends data into the SPI bus. The
paralleloutputsarelatchedinto theparallellatchin-
sidetheL9822ESPattheendofadatatransfer.The
parallelinputs jam diagnosticdata into the shiftre-
gisterat thebeginningof a datatransfercycle.
ParallelLatch
The parallellatchholds theinputdatafrom theshift
register.This datathen actuatestheoutputstages.
Individual registers in the latch may be cleared by
fault conditions in order to protect the overloaded
outputstages.Theentirelatchmayalsobecleared
by theRESET signal.
Output Stages
Theoutputstagesprovidean activelowdrivesignal
suitable for 0.75A continuous loads. Each output
has a currentlimit circuit whichlimits the maximum
outputcurrent to at least1.05Ato allowfor high in-
rushcurrents.Additionally,theoutputshaveinternal
zenersset to 36 voltsto clamp inductivetransients
at turn-off.Each output also has a voltagecompa-
ratorobservingtheoutputnode.If thevoltageexce-
eds 1.8V on an ON output pin, a fault condition is
assumedand the latch driving this particular stage
is reset,turningthe outputOFF to protectit. The ti-
ming of thisaction is describedbelow. Thesecom-
parators also provide diagnostic feedback data to
theshiftregister.Additionally,thecomparatorscon-
tainaninternalpulldowncurrentwhichwillcausethe
cell to indicate a low output voltageif the output is
programmedOFF andtheoutputpinisopencircui-
ted.
TIMINGDATA TRANSFER
Figure #2 showsthe overall timing diagram from a
byte transfer to and from the L9822ESPusing the
SPI bus.
CE Highto Low Transition
TheactionbeginswhentheChipEnable(CE)pinis
pulledlow.Thetri-stateSerialOutput(SO)pindriver
willbe enabledentire timethatCE islow. Atthefal-
lingedgeof theCEpin,thediagnosticdatafromthe
voltagecomparatorsin theoutputstageswillbelat-
ched into the shift register. If a particular output is
high, a logic one will be jammed into that bit in the
shiftregister.Iftheoutputis low,a logiczerowillbe
loadedthere.Themostsignificantbit(07)shouldbe
presentedat theSerial Input (SI) pin. A zeroat this
pin will programan outputON, whilea onewill pro-
gramthe outputOFF.
SCLK Transitions
The Serial Clock (SCLK) pin shouldthenbe pulled
high.Atthispointthediagnosticbitfromthemostsi-
gnificantoutput(07)willappearat theSOpin.Ahigh
here indicates that the 07 pin is higher than 1.8V.
TheSCLKpinshouldthenbetoggledlowthenhigh.
NewSOdatawillappearfollowingeveryrisingedge
of SCLK and new SI data will be latched into the
L9822ESPshiftregisteronthefallingedges.Anun-
limited amount of data may be shiftedthrough the
FUNCTIONAL DESCRIPTION
L9822E
5/11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| L9822EPD | OCTAL SERIAL SOLENOID DRIVER |
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| L9825 | Octal Low-side Driver For Resistive and Inductive Loads With Serial / Parallel Input Control, Output Protection and Diagnostic |
| L9826 | Octal Low-Side Driver for resistive and inductive loads with serial/parallel input control, output protection and diagnostic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L9822EPD | 功能描述:功率驅(qū)動器IC Octal Ser Solenoid RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時間: 下降時間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| L9822EPD013TR | 功能描述:功率驅(qū)動器IC Octal Ser Solenoid RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時間: 下降時間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| L9822ES | 制造商:STMicroelectronics 功能描述: |
| L9822N | 功能描述:電源開關(guān) IC - 配電 OCTAL SOLENOID DRVR RoHS:否 制造商:Exar 輸出端數(shù)量:1 開啟電阻（最大值）:85 mOhms 開啟時間（最大值）:400 us 關(guān)閉時間（最大值）:20 us 工作電源電壓:3.2 V to 6.5 V 電源電流（最大值）: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-23-5 |
| L9822N_03 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:OCTAL SERIAL SOLENOID DRIVER |
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