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參數(shù)資料
| 型號： | L9822ED |
| 廠商： | 意法半導體 |
| 英文描述： | CAP CER 1000PF 1KVDC B RAD |
| 中文描述： | 八路串行電磁驅(qū)動 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 112K |
| 代理商： | L9822ED |
ELECTRICAL CHARACTERISTICS
(Continued)
Symbol
INPUT BUFFER(SI, CE,SCLK and RESETpins)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
T–
Threshold Voltage at
Falling Edge
SCLK only
Threshold Voltage at
Rising Edge
SCLK only
Hysteresis Voltage
Input Current
Input Capacitance
V
CC
= 5V
±
10%
0.2V
CC
0.6
V
V
V
V
T+
V
CC
= 5V
±
10%
0.7V
CC
4.15
2.5
+ 10
20
V
V
μ
A
nF
V
H
I
I
C
I
V
T+
– V
T–
V
CC
= 5.50V, 0 < V
I
< V
CC
0 < V
I
< V
CC
0.85
– 10
OUTPUT BUFFER(SO pin)
V
SOL
V
SOH
Output LOW Voltage
Output HIGH Voltage
I
O
= 1.6mA
I
O
= 0.8mA
0.4
V
V
V
CC
– 1.3V
– 20
I
SOtl
Output Tristate Leakage
Current
Output Capacitance
0 < V
O
< V
CC
, CE Pin Held High,
V
CC
= 5.25V
0 < V
O
< V
CC
CE Pin Held High
All Outputs Progr. ON. I
O
= 0.5A
per Output Simultaneously
20
μ
A
C
SO
20
pF
I
CC
Quiescent Supply
Current at V
CC
Pin
10
mA
SERIALPERIPHERAL INTERFACE (see fig. 2, timingdiagram)
f
op
t
lead
t
lag
t
wSCKH
t
wSCKL
t
su
t
H
t
EN
t
DIS
t
V
t
rSO
t
fSO
t
rSI
Operating Frequency
Enable Lead Time
Enable Lag Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Enable Time
Disable Time
Data Valid Time
Rise Time (SO output)
Fall Time (SO output)
Rise Time SPI
Inputs (SCK, SI, CE)
Fall Time SPI
Inputs (SCLK, SI, CE)
Output Data Hold Time
D.C.
250
250
200
200
75
75
250
250
100
2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
CC
= 20 to 70% C
L
= 200pF
V
CC
= 70 to 20% C
L
= 200pF
V
CC
= 20 to 70% C
L
= 200pF
50
50
200
t
fSI
V
CC
= 70 to 20% C
L
= 200pF
200
ns
t
ho
0
μ
s
L9822E
4/11
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