參數(shù)資料
型號(hào): L7585F
英文描述: Full-Feature,Low-Power SLIC and Switch
中文描述: 全功能,低功耗SLIC和開(kāi)關(guān)
文件頁(yè)數(shù): 5/22頁(yè)
文件大?。?/td> 441K
代理商: L7585F
Agere Communications Inc.
5
Data Sheet
September 2001
L7585F Full-Feature, Low-Power SLIC and Switch
Pin Information
(continued)
Table 1. Pin Descriptions
Note: On the printed-wiring board (PWB), make the leads to BGND and V
BAT
as wide as possible for thermal and electrical reasons. Also, max-
imize the amount of PWB copper on all leads connected to this device for the lowest operating temperature.
Pin
1
2
Symbol
V
CCA
LCTH
Type
I
Name/Function
+5 V Analog dc Supply.
+5 V supply for analog circuitry.
Loop Closure Threshold Input.
Connect a resistor to DC
OUT
to set the off-hook thresh-
old.
Current-Limit Program Input.
A resistor to DC
OUT
sets the dc current limit.
dc Output.
This output is a voltage that is directly proportional to the differential
tip/ring current.
dc Resistance.
Ground for dc feed resistance of 180
, or short to DC
OUT
for 600
. In-
termediate values can be set with a resistor divider from DC
OUT
to ground, the tap of which
is connected to DCR.
Filter Capacitor 2.
Connect a 0.1 μF, 100 V capacitor from this pin to AGND and a
0.22 μF, 100 V capacitor from this pin to pin CF1.
Filter Capacitor 1.
Connect a 0.22 μF, 100 V capacitor from this pin to pin CF2.
Forward Battery Slowdown 2.
A capacitor from FB1 to AGND and from FB2 to AGND
will ramp the polarity reversal transition when quiet polarity reversal is required. If not
needed, the pin can be left open.
Forward Battery Slowdown 1.
A capacitor from FB1 to AGND and from FB2 to AGND
will ramp the polarity reversal transition when quiet polarity reversal is required. If not
needed, the pin can be left open.
Battery Ground.
Ground return for the battery (V
BAT
) supply.
Battery Supply.
Negative high-voltage power supply.
Battery Supply.
Negative high-voltage power supply.
+10 V Supply.
+10 V bias supply for switch circuitry.
Not Channel Select.
A low-to-high transition on this logic input stores the data on pins
B0—B5 into the input latches on the SLIC. When NCS is either high or low, the SLIC is
unaffected by data on pins B0—B5.
Clock.
Clock input.
Not Detect.
When low, this logic output indicates either a ring trip or an off-hook condition,
depending on the input state of the SLIC. If either the BCDMOS portion or CBIC portion
of this device enters thermal shutdown, NDET will be forced low.
Digital Ground.
Ground return for V
CCD
and relay driver flyback current.
Relay Driver.
This output drives an external relay. RDO is low (relay operated) when a
low input on B5 is latched into the SLIC.
Ring Trip Sense.
Sense input for the ring trip detector.
Ring Lead Ringing Access Switch.
Ringing relay connects this pin to pin RRNG. Con-
nect this pin to pin PR through a 500
current-limiting resistor.
Ring Lead Ringing Supply.
Connect this pin to the ringing supply.
Protected Ring.
The output of the ring driver and input to the transmit current sense cir-
cuit. Connect to the ring of the loop through overvoltage protection.
3
4
I
PROG
DC
OUT
I
O
5
DCR
I
6
CF2
I/O
7
8
CF1
FB2
I/O
I
9
FB1
I
10
11
12
13
14
BGND
V
BAT
V
BAT
V
SP
NCS
I
15
16
CLK
NDET
I
O
17
18
DGND
RDO
O
19
20
RTS
RSW
I
O
21
22
RRNG
PR
I
I/O
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