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參數(shù)資料
| 型號： | L6996D |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封裝： | MO-153AD, TSSOP-24 |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 272K |
| 代理商： | L6996D |
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L6996
18/26
Table 2. PCB Layout guidelines
3
DESIGN EXAMPLES
3.1 VIN = 20V IOUT = 23A
In this design it is considered a low profile demoboard, so a great attention is given to the components height.
3.2 Input capacitor
A pulsed current (with zero average value) flows through the input capacitor of a buck converter. The AC com-
ponent of this current is quite high and dissipates a considerable amount of power on the ESR of the capacitor:
Eq 15
The IRMS current is given by:
Eq 16
Neglecting the last term, the equation reduces to:
Eq 17
PCIN, and also ICINRMS, has a maximum equal to IOUT/2 (@ VIN =2 × VOUT, that is, 50% duty cycle). The input,
therefore, should be selected for a RMS ripple current rating as high as half the respective maximum output
current. Electrolytic capacitors are the most used because are the cheapest ones and are available with a wide
range of RMS current ratings. The only drawback is that, considering a requested ripple current rating, they are
physically larger than other capacitors. Very good tantalum capacitors are coming available, with very low ESR
and small size. The only problem is that they occasionally can burn out if subjected to very high current during
the charge. So, it is better avoid this type of capacitors for the input filter of the device. In fact, they can be sub-
jected to high surge current when connected to the power supply. If available for the requested value and volt-
age rating, the ceramic capacitors have usually a higher RMS current rating for a given physical size (due to the
very low ESR). From the equation 17 it is found:
Goal
Sugg estion
Low radiation and low magnetic coupling with the
adjacent circuitry
1) Small switching current loop areas. (For example Placing
CIN, high side and Low Side MOSFET,Schottky diode, as
close as possible each to others).
2) Controller placed as close as possible to the Power
MOSFET.
3) Group the gate drive component (Boot cap and diode
together near the IC.
Don’t penalty the efficiency
Keep the power traces and load connections short and wide.
Ensure high accuracy in the current sense system
Cs+, CS- traces must be made by Kelvin connection. Also the
traces should be separated from the power plane by a ground
plane, run parallel.
Reduce the noise effects on IC
1) Put the feedback component (like the VP network as close
as possible to the IC)
2) The feedback connection (like the FB trace, or CS+/CS-
traces
….) should be route as far as possible from the
switching current loops.
3) Make the controller ground connection like in the figure 16.
P
CIN
ESR
CIN
Iout
2
Vin
Vout
–
()
Vin
2
----------------------------------------------- -
=
Ic in
rms
I out
2δ 1 δ
–
()
δ
12
------
I
L
()
2
+
=
Ic in
rms
Iout
δ 1 δ
–
()
=
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