參數(shù)資料
型號: L6726A
廠商: 意法半導(dǎo)體
英文描述: Single phase PWM controller
中文描述: 單相PWM控制器
文件頁數(shù): 18/24頁
文件大?。?/td> 399K
代理商: L6726A
Application details
L6726A
18/24
The previous equation refers only to V
OUT
ramp up time. The time elapsed from the end of
OC setting phase or COMP set free to the beginning of V
OUT
ramp up (see
Figure 6
) can be
approximately estimated as follow:
Once calculated t
SS
, also the current delivered by the converter during SS to charge the
output capacitor bank can be estimated:
8.4
Layout guidelines
L6726A provides control functions and high current integrated drivers to implement high-
current step-down DC-DC converters. In this kind of application, a good layout is very
important.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure 10
) must be a part of a power plane and anyway realized by wide and thick copper
traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs,
must be close one to the other. The use of multi-layer printed circuit board is recommended.
Figure 10.
Power Connections (heavy lines)
The input capacitance (C
IN
), or at least a portion of the total capacitance needed, has to be
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.
Use proper VIAs number when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
Connect output bulk capacitors (C
OUT
) as near as possible to the load, minimizing parasitic
inductance and resistance associated to the copper trace, also adding extra decoupling
capacitors along the way to the load when this results in being far from the bulk capacitors
bank.
Gate traces and phase trace must be sized according to the driver RMS current delivered to
the power MOSFET. The device robustness allows managing applications with the power
t
delay
C
--------------------------
0.8V
I
SS
=
I
startup
C
------------------------------------
V
t
SS
=
L
C
IN
V
IN
UGATE
PHASE
LGATE
GND
LOAD
L6726A
C
OUT
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