參數(shù)資料
型號(hào)： L6714TR
廠商： 意法半導(dǎo)體
英文描述： 4 phase controller with embedded drivers for Intel VR10, VR11 and AMD 6Bit CPUs
中文描述： 4英特爾VR10，VR11和AMD的6位嵌入式CPU的司機(jī)相控制器
文件頁(yè)數(shù)： 47/70頁(yè)
文件大小： 572K
代理商： L6714TR
L6714
Output voltage monitor and protections
47/70
16
Output voltage monitor and protections
L6714 monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP
and PGOOD (when applicable) conditions. The device shows different thresholds when
programming different operation mode (Intel or AMD,
See Table 10
) but the behavior in
response to a protection event is still the same as described below.
Protections are active also during soft-start (
See “Soft start” Section
) while are masked
during D-VID transitions with an additional 32 clock cycle delay after the transition has
finished to avoid false triggering.
16.1
Under voltage
If the output voltage monitored by VSEN drops more than -750mV below the programmed
reference for more than one clock period, L6714 turns off all MOSFET and latches the
condition: to recover it is required to cycle Vcc or the OUTEN pin. This is independent of the
selected operative mode.
16.2
Preliminary over voltage
To provide a protection while VCC is below the UVLO
VCC
threshold is fundamental to avoid
damage to the CPU in case of failed HS MOSFET. In fact, since the device is supplied from
the 12V bus, it is basically “blind” for any voltage below the turn-on threshold (UVLO
VCC
). In
order to give full protection to the load, a preliminary-OVP protection is provided while VCC
is within UVLO
VCC
and UVLO
OVP
.
This protection turns-on the low side MOSFET as long as the FBR pin voltage is greater
than 1.800V with a 350mV hysteresis. When set, the protection drives the LS MOSFET with
a gate-to-source voltage depending on the voltage applied to VCCDRx and independently
by the turn-ON threshold across these pins (UVLO
VCCDR
). This protection depends also on
the OUTEN pin status as detailed in
Figure 18
.
A simple way to provide protection to the output in all conditions when the device is OFF
(then avoiding the unprotected red region in
Figure 18-Left
) consists in supplying the
controller through the 5V
SB
bus as shown in
Figure 18-Right
: 5V
SB
is always present before
+12V and, in case of HS short, the LS MOSFET is driven with 5V assuring a reliable
protection of the load. Preliminary OVP is always active before UVLO
VCC
for both Intel and
AMD Modes.
Figure 18. Output voltage protections and typical principle connections
VCC
VCCDR1
VCCDR2
VCCDR3
+12V
+5V
SB
Vcc
UVLO
OVP
UVLO
VCC
Preliminary OVP Enabled
FBR Monitored
No Protection
Provided
(OUTEN = 1)
Programmable OVP
VSEN Monitored
(OUTEN = 0)
Preliminary OVP
FBR Monitored
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