
Symbol
A/D CONVERTER TIMINGS
T
cscks
Conv. start set uptime
T
csckh
Conv. Start hold time
T
ckout
Falling edge of clock to data
out valid delay
T
csz
ConvStart falling edge to output
in Hi-Z delay
F
adck
Clock frequency
T
cslow
Conv. Start low level time
T
acq th
Theoretical acquisition time
T
acqpr
Real acquisition time
DIGITAL INTERFACE INPUT
V
inp
Schmitt Trigger positive-going
Threshold
V
inm
Schmitt Trigger negative-going
Threshold
V
hys
Scmitt Trigger Hysteresis
I
in
Input Current (Vin=0; Vdd=5)*
Parameter
Test Condition
Min.
Typ.
Max.
Unit
200
200
ns
ns
ns
C
load
≤
20pF
200
200
ns
250
KHz
μ
s
μ
s
μ
s
5.6
32.4
36
f
adck
= 250 kHz
f
adck
= 250 kHz
2/3V
dd
V
1/3V
dd
V
0.1
50
0.3
150
1
V
μ
A
300
* This applies to input pins having an internal pull-up (ENABLE_CHANNEL,LONG_PULSE, SHORT_PULSE)
CR LATCH TIMINGS
T
ls
T
lhigh
T
lconv
Latch set up time
Latch high time
Latch data valid to A/D input
valid delay
100
100
ns
ns
Selected channel:
CH1..CH5
CH0
4
7
μ
s
μ
s
NB: The control register (driving signals CRdata, CRclock) is accessed with the same timing specifications as the
data 16 bit shift register (signals Serial data, Serial clock)
SHIFT REGISTER AND LATCH TIMING
T
a
Set up time
T
b
Hold time
T
c
Serial clock low time
T
d
Serial clock high time
T
e
Serial clock period
T
f
Latch set up time
T
g
Latch data high time
T
set
Long Pulse set_up time with
respect to NCEn
T
hold
Long Pulse hold time with
respect to NCEn
OUTPUTS ELECTRICAL CHARACTERISTICS
I
out
Output Current (outputs 0..15)
50
50
50
50
150
100
100
160
ns
ns
ns
ns
ns
ns
ns
ns
0
ns
DC=33%;
preheating DC=66%
T
j
= 25
°
C
From 50% Long Pulse to 90%
power output rising edge
Load = 30 Ohm in parallel with
1.5nF
From 50% Long Pulse to 90%
power output falling edge
Load = 30 Ohm in parallel with
1.5nF
400
mA
ns
R
ds(ON)
T
on
On Resistance
Turn on Time (Tdelay + Trise)
1.3
160
T
off
Toff delay time
100
ns
DC ELECTRICAL CHARACTERISTICS
(T
j
= 25
°
C)
L6452
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