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參數(shù)資料
| 型號： | L6372 |
| 英文描述： | OCTAL INDUSTRIAL INPUT INTERFACE(253.91 k) |
| 中文描述： | 八路工業(yè)輸入接口（253.91十一） |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 253K |
| 代理商： | L6372 |
Present
State
000
000
001
001
010
010
011
011
100
100
101
101
110
110
111
111
Filter
Output
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Input
Next State
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
000
001
000
010
000
011
000
100
101
100
110
100
111
100
000
100
It can be seen, for instance, that pulses of the in-
put, with a polarityopposite to the output and last-
ing for less than four clock periods, are com-
pletely filtered out.
If instead the input exhibits a change of level that
lasts long enough for four clock edges to sample
it, then the output of the filter, after the four clock
periods,follows the change of level at the input.
If an input signal with changes that do not occur
more often that every 32 periods of the main os-
cillation is considered,it can be seen that such fil-
ter introduces a delay of the input transitionsthat
is randomly variable from 24 to 32 periods of the
mainoscillation.
In the case of input transitionsthat occur closer to
each other than 24 periods of the oscillator, the
resulting pulse is considered an unwanted noise
pulse and is consequentlyeliminated by the filter.
An input pulse lasting between 24 and 32 periods
could either be cancelled or acknowledgedby the
filter, with the delay said above, according to the
relative phase of such pulse with respect to the
squarewave (clock/8) that clocks the filter.
DEVICE OUTPUT
To extract the information from the L6372 (line le
vels or line statuses according to the Dt/Dg pin)
the external processor activates the following se-
quence:
1)The level on pin P/S (Parallel active high / Se-
rial active low) is broughtfrom its normal high
levelto a low logical level.
The parallel jam inputs to the 8 flip-flops of
the shift register are disabled.The last datum
availableis kept in each cell.
The output of the first cell of the shift register
is made available on the output pin Dout.
When the L6372 is in parallel mode, Dout is
kept at its low level, irrespectively of the out-
put of the shift register.
The signals on the L6372 inputs Clk and Din
are made available on the relevant internal
inputs to the shift register.
2)The external processor can now startclocking
the shift register.
At every rising edge of the signal on the Clk
pin, the data are shifted one step forward. In
a typicalcase, severalL6372 are chained to-
gether. The clock signal is
Dout of thefirst is connectedto theDin of the
second, and so on, so that the external proc-
essor can, with a single shift operation, read
the data of all the devices chained together,
from the output Dout of the last in the chain.
common. The
RESET
An internal reset signal is generated any time an
anomalous condition is detected, and used to
block the device operation.
Suchreset signal is generatedwhen one (or both)
of the following conditions is detected:
- undervoltage
- overtemperature
It inhibits the serial output,resets the shift register
and the digital filters, but has no effect on the
creation of the reference voltages of the internal
comparators, nor on the continuous operation of
the oscillator.
The reset disappears one or two clock pulses af-
ter the overtemperatureor undervoltagecondition
has disappeared.
UNDERVOLTAGE DETECTION
The supply voltageis expectedto range from12V
to 30V, even if its referencevalue is consideredto
be 24V.
In this range the L6372 operates correctly. Below
12V the overall system has to be considered not
reliable. Consequentlythe supply voltage is moni-
tored continuously and a signal, called UV, is in-
ternally generatedand used.
The signal is ”on” as long as the supply voltage
does not reachthe upper internal thresholdof the
V
s
comparator (called V
sh
and typically found at
10.4V).TheUV disappearsabove V
sh
.
Once the UV has been removed, the supply volt-
age must decrease below the lower threshold
(called V
sl
, and typically set at 10.2V) before it is
turnedon again.
The hysteresis of approximately 800mV is pro-
vided to prevent intermittent operation of the de-
vice at low supply voltages that may have a su-
perimposedripplearound the average value.
L6372
11/15
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