given application is too slow. Figure 4-9 is an os-
cillograph taken on a device that had a fairly large
value for Rslew and failed to spin up and phase
lock a motor.
The problem manifests itself as the motor begins
to spin up. At lower RPMs, the Bemf of the motor
is relatively small resulting in higher amounts of
commutation current. In figure 4-9, the upper
waveform is the voltage appearing at OUTPUT
relative to the CENTER TAP input. The lower
waveform is the actual output of the Bemf ampli-
fier available on special engineering prototypes.
The oscillograph was taken just as the problem
occured. The period between zero crossings was
~800
s resulting in a mask time period of 200s.
As can be seen, the excessively long slew rate
actually exceeded the mask period and was de-
tected as a zero crossing.
This resulted in improper sequencing of the out-
puts relative to the proper phases and caused the
motor to spin down.
4.7 Ext PFET Driver
The power handling capabilities of the 3 phase
output stage can be extended with the addition of
a single P-Channel FET.
Figure 4-10 shows the Ext FET connection and
demonstrates how the L6238S automatically
senses the FETs presence. When the voltage at
the Gate Drive pin is
≥ 0.7V, the output of com-
parator A3 goes high, removing the variable drive
A1 from the internal FETs and connects them in-
stead to Vanalog via the commutation switches to
facilitate full conduction.
The upper FETs drive paths are not shown for
clarity. A3 also closes SW2 allowing A1 to linearly
drive the external P-Channel FET Q1 via inverter
A2.
4.8 Bemf Ampolifier
Since no Hall Effect Sensors are required, the
commutation information is derived from the Bemf
voltage zero-crossings of the undriven phase with
respect to the center tap. The Bemf comparator
and associated signal levels are depicted in figure
4-11. For reliable operation, the Bemf signal am-
plitude should be a minimum of
± 60 mV to be
properly detected. In order to provide for noise
immunity, internal hysteresis is incorporated in
the detection circuitry to prevent false zero cross-
ing detection.
For laboratory evaluation purposes, a simple re-
Figure 4-10: External P-Fet.
L6238S
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