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參數(shù)資料
| 型號(hào)： | L6223A |
| 文件頁(yè)數(shù)： | 9/33頁(yè) |
| 文件大?。?/td> | 1335K |
| 代理商： | L6223A |
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ing diagram for programming. When the inputs
IN1...IN4 are together Low a clock pulse is gener-
ated internally which clocks a data bit into the
shift register. If the time interval during which all
four inputs are Low is less than 0.2
μ
s, no clocks
pulse in generated thus preventing undesirable
programming. To generateanother clock pulse at
least one of the four inputs must first go High and
then Low again. The first bit is loaded into C0 and
after 6 clock pulse it will be in the C5 posistion.
Two programming technique are suggested. The
first (Fig. 8) uses IN4 in such a way that the
power section is disabled the total programming
time (the carriage of the 6 programmingbits). Fig.
9 shows another technique:the motordriving sig-
nals at the inputs IN1...IN4 are interruptedswitch-
ing IN1...IN4 Low to carry a single bit. This per-
mits the motor to be enabled for the 50% of total
programming time. During the motor rotation it’s
suggested to program the device immediately af-
ter the motor phase change: this make neglect-
able the motor driving discontinuitydue to the de-
vice programming.
Figure8:
Waveformfor programming:theoutputis disabledduringall theprogramming duration(seeTable 4).
Figure9:
Waveformfor programming:the output is disabled onlywhen all four inputs are at thelow level.
L6223A
9/33
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