參數(shù)資料
型號： L6223A
文件頁數(shù)： 5/33頁
文件大?。?/td> 1335K
代理商： L6223A
ELECTRICAL CHARACTERISTICS
(Continued)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
SWITCHING TIMING
t2, t4
Fall/Rise Time (IN1, 2, 3, 4)
R
(load)
= 39
(Fig. 5)
Pure Resistive Load to V
S
250
ns
t1, t3
Input-Output Delay
(IN1, 2, 3, 4)
R
(load)
= 39
(Fig. 5)
Pure Resistive Load to V
S
700
ns
t
dPWM
Close Loop PWM
Control Delay
(Fig. 4) Note 1
1
μ
s
PROGRAMMING TIMING
t1
Loading Time
(Fig. 6)
1.7
μ
s
t2
Protection Time
(Fig. 6) Note 2
0.2
μ
s
t3
Data Set-up
(Fig. 6)
0
ns
t4
Data Hold
(Fig. 6)
1.6
μ
s
t5
Setting Time
(Fig. 6)
200
ns
Note 1) Upper DMOS turn ON delay when the signal is applied at the input comparator (pointA in Fig. 4).
Note 2) Internal clock pulseis generated only if IN1...IN4 stay Low foralmost 0.2
μ
s. This delay avoids undesirable programmings.
Figure1:
Outputleakage I
OL
TestCircuit
Figure 2a:
SourceOutput DMOS R
DS(ON)
Test
Circuit
L6223A
5/33
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