
BLOCKDIAGRAM DESCRIPTION
InputLogic
Decodes the input signals IN1, IN2, IN3, IN4,
DA/OPLO, and DA/CLEV for programming the
device and driving the motor. The six inputs are
CMOS compatible and can interface directly with
a microprocessor.
PredriverStages
Drive the gates of the five DMOS. They interface
the power section with the logic section. The in-
ternal inhibit, when activated, disables the power
section. The reset initializes the shift register and
disables the power section.
6 bit ShiftRegister
Internal memory which defines the working con-
figuration of the device along with the input sig-
nals.
Current Control
When selected with the input DA/OPLO = L
(Closed Loop), it will maintain a constant output
current level by chopping. The value of the refer-
ence voltage, which is compared to the sense
voltage, is given by the Ref Block. The chopping
frequencydepends on bit C4.
Ref Block
Defines the current chopping level according to
bits C0 andC1 and the input signals.
Fixed on Time
When selected with DA/OPLO = H, it will define
accordingto bits C2 and C3 thechopping duty cy-
cle for the Open Loop mode. The chopping fre-
quencyis fixed.
Oscillator
Provides the clock setting the S/R FLIP-FLOP
that turn ON/OFF the upper DMOS (Fig. 22). The
higher operative chopping frequencyis defined by
the external RC network (typically 20KHz). At the
phase change a syncronous clock pulse is gener-
ated
Reset Logic Block
Generates the reset signal for the logic at power
on and disables the outputs. The reset can also
be generated externally by setting the RC pin to
less that 0.9V.
ThermalProtection
Disables the power section in case of over tem-
peraturecondition.
Charge Pump
Along with an external bootstrap capacitor con-
nected between the BSTP and COM pins, this
block generates the internal over voltagerequired
to drive the upperDMOS on.
PowerOutput
Driven by the Predriver Stages, it supplies the
power for the motorwindings.
CIRCUIT OPERATION
The five N DMOS transistors of the output stage
drive the unipolar motor windings, controlling the
current by chopping. In particular, the four Low
side (OUT1, OUT2, OUT3, OUT4) switch the
phase configurations, and the High side DMOS
(COM) is for chopping control.
For this transistor a charge pump circuit provides
its necessarygate drive overvoltage.
The microprocessor outputs are interfaced with
the L6223 output stages through the input logic
block. This block also protects the devicefrom mi-
croprocessor output errors and failures from the
power section back to the microprocessor out-
puts. The six digital inputs IN1, IN2, IN3, IN4,
DA/CLEV, DA/OPLO, are decoded for motor con-
trol and rotation when in ”O(jiān)perating mode” and
used for the internal six Bit memory programming
when in ”ProgrammingMode”.
Table 1 shows the condition that selects these
device status. The programmingof the internal six
bit memory setsoperative conditionssuch as:
PWMCURRENT LEVELS
CHOPPINGFREQUENCY
LOGICIN/OUT DECONDING
This memory works like a shift register.Each bit is
introduced serially by decoding the IN1, IN2, IN3,
IN4 low status for the internal clock pulse genera-
tion and by the DA/CLEV DA/OPLO, inputs in
exor, as datain.
Figure 7 shows the six bit meaning.
In the operatingmode twodifferent input drive are
possible. In SIMPLIFIEDOPERATING MODE the
IC needs few logic wire for the motor rotation, but
only the full step driving sequence can be per-
formed.
L6223
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