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參數(shù)資料
| 型號： | L6213 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SOLENOID DRIVER SWITCH MODE POWER SUPPLY |
| 中文描述： | 電磁驅(qū)動開關(guān)電源 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 136K |
| 代理商： | L6213 |
PIN DESCRIPTION
Nr.
1
2
Name
Out-Up
BSE
Description
Solenoid section upper DMOS output.
Solenoid section upper DMOS bootstrap. A capacitor connected between pin 2 and pin 1
ensures the efficientdriving of the solenoid section upper DMOS.
Solenoid control input - TTL compatible.
Unregulated voltage input - Solenoid section.
Ground.
Power fail output, the saturation of PF is guaranteed if VPS exceed 3V. PF is at logic 1 a
time T
1
after RESET reachedthe high level. PF came back to logic 0 when VPS goes
down under 18V. (see fig. 1)
Power fail programming. A resistordivider connected to VPS changesthe Power fail
threshold levels.
Capacitor delay. A capacitor connected to this pin determines the Reset signal delay time
t
d
.
Unregulated voltage input - SMPS sections.
Regulator output and diode voltage control.
SMPS section DMOS bootstrap. A capacitor connected between pin 12 and pin 11
ensures efficient driving of SMPS DMOS.
Reset output. The saturation of Reset is guaranteed if VPSexceeds 3V. The Reset output
reaches the logic level 1 a time delay (set by capacitorCD) after VPS has reached a
rising threshold voltage. Reset reaches 0 level when VPS goes down belowfolling
threshold.
Feed backinput of the regulation loop.
Ground.
Connection for solenoid sensing resistor.
Programming of solenoid current rising edge. An RC network connected to this pin
determines the slope of the solenoid current rising edge.
Programming of solenoid current histeresys.
Solenoid section lower DMOS output.
3
4
ENABLE
+V
S1
GND
PF
5, 6
7
8
PFP
9
CD
10
11
12
V
S2
VD
BSA
13
RESET
14
V
out
GND
R
sense
PIM
15, 16
17
18
19
20
ISTP
Out-Down
ELECTRICAL CHARACTERISTICS
(Refer to the application circuit, T
J
=25
°
C, I
out
Power Supply =
50mA, VPS from 12V to 46V; unlessotherwise specified.
Pin
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
STEP-DOWNSECTION
10, 4
14
V
i
V
o
Supply Voltage
Output Voltage
On State Drain Resistance
Turn-on Threshold
Turn-off Threshold
Input Bias Current
Static Current Limiting
Total Input Current
14
4.85
46
5.2
0.7
12
12
15
3.4
13
V
V
V
V
mA
A
mA
I
O
= 0.05 to 1A
T
J
= 25
°
C; VPS = 15 to 46V
VPS Rising Fig. 1
VPS Falling Fig. 1
R
DS on
t
h on
t
h off
I
B
I
lim
I
i
0.56
10
10
10
11
10
10
2.2
2, 10
ENABLE = 1, VPS = 46V,
I
load
= 0
ENABLE = 1, VPS = 15V,
I
load
= 0
2, 10
I
i
Total Input Current
18
mA
11
t
dp
Protection Current Maximum
Delay Time
Minimum Power off State
1
μ
s
t
off
VPS = 46V I
O
= 50mA
4.2
7.8
μ
s
L6213
4/9
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