參數(shù)資料
型號(hào)： L3000N
廠商： 意法半導(dǎo)體
英文描述： Subscriber Line Interface(用戶線路接口設(shè)備)
中文描述： 用戶線接口（用戶線路接口設(shè)備）
文件頁(yè)數(shù)： 11/28頁(yè)
文件大?。?/td> 374K
代理商： L3000N
Ringing Mode
Whenringingisselected(BIT2R=1,BIT0R=0),the
control unit L3030 presets the L3000N to operate
between– 48V(– 60V) and + 72V (+ 60V) battery.
Then,settingBIT1=1,alowlevelsignal(0.285Vrms
with frequency range16-66Hz)applied to pin 41, is
amplified and injected in balanced modeto the line
throughL3000NwithasuperimposedDC voltageof
24V.The impedance to the line is given by the two
externalresistors andthe 24V DC polarity can only
be direct.
Thefirstandthelastringingcyclesaresynchronized
byL3030 so that ringing alwaysstarts and stops at
zero crossing. Ring trip detectionis performed au-
tonomouslybytheSLIC,withoutanyparticularcom-
mand, using a patentedsystem ; whenhandset is
lifted, SLIC suspendsthe ringing signal just remai-
ningintheringingmode.Inthiscondition,thecontrol
unit L3030checksthatthe loop is closed for a time
equalto twoperiods oftheringing signal ; if the clo-
sureis confirmed,a flag(BIT0T = 1) is setand the
SLIC waits the new commandfrom the control pro-
cessor.Whereasthe loop closure is not confirmed,
theringingsignalis newlyappliedto theline, without
settingBIT0T.
DIGITAL INTERFACE
Functional Description
The L3030 states and functions are controlled by
centralprocessor throughfive wires defining a digi-
talinterface.Itispossibletoselecttheinterfacewor-
kingmodebetweenSERIAL or PARALLEL(pin 33
tied to a voltage between4 and 5V).
1) SerialMode
The five wires of the digital interfacehavethe follo-
wing functions:
- clock(DCLK), entering at pin 21
- datain/data out (DIO), exchangedat pin20
- input/outputselect (EIA), enteringat pin 18
- chipselect (NCS), enteringat pin 19
- changeNCS fromin to out(CI), enteringatpin26
(note 1)
The maximum clock frequencyis 600Khz.
WhenEIAsignalislowdataaretransferredfromthe
cardcontroller into I/Oregistersof the L3030selec-
ted by NCS signal tied at low level ; then data are
latchedfor execution.In thisphasea complete8 bit
wordisloadedintointernalregisterandconsequen-
tly NCS signal must remain low for the correspon-
ding 8 clock pulses (DCLK). The EIA signal must
remainatlow levelatleastforthetimeinwhichNCS
signalremain low. The device load datain input re-
gister during the positive edge of clock signal
(DCLK)andstorethecontentsof theregisteronthe
positiveedge of NCS signal.
When EIA signal is high data are transferred from
the L3030 selected by NCS tied to low level to the
card controller. The L3030 status is described by
five bits contained in the output register ; the NCS
signalcanremainlowforfiveor lessclockpulsesde-
pendingif the card controllerwant to read the com-
plete L3030statusor only a part of it.
Fig.8,9showthecompletewrite andreadoperation
timing. Table1showsthe meaningofeachbit ofan
I/O data.
L3000N - L3030
11/28
相關(guān)PDF資料
PDF描述
L3030 Subscriber Line Interface(用戶線路接口設(shè)備)
L3000S SLIC Kit Optimized for Applications with Both First and Second Generation Combos(用于短波/超短波通信系統(tǒng)的用戶線接口)
L30030G-1 Class G Fuse Blocks
L30030G-2 Class G Fuse Blocks
L30030G-3 CAP CER 1.5UF 50V Y5V 1812
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