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參數(shù)資料
| 型號： | L29S800F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8MEGABIT (1M】8 /512K】16) 3 VOLT CMOS FLASH MEMERY |
| 中文描述： | 8MEGABIT（100萬】8 / 16】為512k）3伏的CMOS閃存MEMERY |
| 文件頁數(shù)： | 22/54頁 |
| 文件大?。?/td> | 797K |
| 代理商： | L29S800F |
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L29S800F
PRELIMINARY
A
8MEGABIT (1M×8 /512K×16)
3 VOLT CMOS FLASH MEMERY
LinkSmart
DQ
7
Data
Polling
The L29S800F/-B devices feature
Data
Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read
the devices will produce the complement of the data last written to DQ
7
. Upon completion of the
Embedded Program Algorithm, an attempt to read the device will produce the true data last written to
DQ
7
. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ
7
output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a
“1” at the DQ
7
output. The flowchart for
Data
Polling (DQ
7
) is shown in Figure 22.
For chip erase and sector erase, the
Data
Polling is valid after the rising edge of the sixth
WE
pulse
in the six write pulse sequence.
Data
Polling must be performed at sector address within any of the
sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the
Embedded Algorithm operation is close to being completed, the L29S800F/-B data pins (DQ
7
) may
change asynchronously while the output enable (
OE
) is asserted low. This means that the devices are
driving status information on DQ
7
at one instant of time and then that byte’s valid data at the next instant
of time. Depending on when the system samples the DQ
7
output, it may read the status or valid data.
Even if the device has completed the Embedded Algorithm operation and DQ
7
has a valid data, the data
outputs on DQ
0
to DQ
6
may be still invalid. The valid data on DQ
0
to DQ
7
will be read on the successive
read attempts.
The
Data
Polling feature is only active during the Embedded Programming Algorithm, Embedded
Erase Algorithm or sector erase time-out. (See Table 9.)
See Figure 9 for the
Data
Polling timing specifications and diagrams.
DQ
6
Toggle Bit I
The L29S800F/-B also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (
OE
toggling)
data from the devices will result in DQ
6
toggling between one and zero. Once the Embedded Program or
Erase Algorithm cycle is completed, DQ
6
will stop toggling and valid data will be read on the next
successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth
WE
pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid
after the rising edge of the sixth
WE
pulse in the six write pulse sequence. The Toggle Bit I is active
during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 ms and
then stop toggling without the data having changed. In erase, the devices will erase all the selected
sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle
the toggle bit for about 100 μs and then drop back into read mode, having changed none of the data.
Either
CE
or
OE
toggling will cause the DQ
6
to toggle. In addition, an Erase Suspend/Resume
command will cause the DQ
6
to toggle.
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
22
071802
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