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參數(shù)資料
| 型號(hào)： | KSZ9021RN-EVAL |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 51/58頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR KSZ9021RN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，以太網(wǎng)控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ9021RN |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 576-3978-ND - IC TXRX 10/100/1000 SGL 48QFN 576-3637-ND - IC TXRX 10/100/1000 SGL 48QFN |
| 其它名稱： | 576-3874 |
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2010 Microchip Technology Inc.
DS22265A-page 55
MCP444X/446X
6.2.1.4
Repeated Start Bit
The Repeated Start bit (see Figure 6-5) indicates the
current Master Device wishes to continue communicat-
ing with the current Slave Device without releasing the
I2C bus. The Repeated Start condition is the same as
the Start condition, except that the Repeated Start bit
follows a Start bit (with the Data bits + A bit) and not a
Stop bit.
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
FIGURE 6-5:
Repeat Start Condition
Waveform.
6.2.1.5
Stop Bit
The Stop bit (see Figure 6-6) Indicates the end of the
I2C Data Transfer Sequence. The Stop bit is defined as
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I2C interface of all MCP44XX
devices.
FIGURE 6-6:
Stop Condition Receive or
Transmit Mode.
6.2.2
CLOCK STRETCHING
“Clock Stretching” is something that the receiving
Device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP44XX will not stretch the clock signal (SCL)
since memory read access occur fast enough.
6.2.3
ABORTING A TRANSMISSION
If any part of the I2C transmission does not meet the
command format, it is aborted. This can be intentionally
accomplished with a START or STOP condition. This is
done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
FIGURE 6-7:
Typical 8-Bit I2C Waveform Format.
FIGURE 6-8:
I2C Data States and Bit Sequence.
Note 1:
A bus collision during the Repeated Start
condition occurs if:
SDA is sampled low when SCL goes
from low to high.
SCL goes low before SDA is asserted
low. This may indicate that another
master is attempting to transmit a
data "1".
SDA
SCL
Sr = Repeated Start
1st Bit
SCL
SDA A / A
P
1st Bit
SDA
SCL
S
2nd Bit 3rd Bit
4th Bit 5th Bit 6th Bit
7th Bit
8th Bit
P
A / A
SCL
SDA
START
Condition
STOP
Condition
Data allowed
to change
Data or
A valid
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