參數(shù)資料
型號(hào)： KSZ8995FQI
廠商： Micrel Inc
文件頁(yè)數(shù)： 89/89頁(yè)
文件大?。?/td> 0K
描述： IC SWITCH 10/100 5PORT 128-PQFP
標(biāo)準(zhǔn)包裝： 66
系列： *
產(chǎn)品目錄頁(yè)面： 1081 (CN2011-ZH PDF)
配用： 576-3872-ND - BOARD EVALUATION FOR KSZ8995FQ
其它名稱(chēng)： 576-3300
Micrel, Inc.
KS8995MA/FQ
October 2011
9
M9999-102611-3.0
List of Figures
Figure 1. Broadband Gateway ............................................................................................................................................ 11
Figure 2. Integrated Broadband Router .............................................................................................................................. 11
Figure 3. Standalone Switch ............................................................................................................................................... 12
Figure 4. Using KS8995FQ for Dual Media Converter or Fiber Daisy Chain Connection .................................................. 12
Figure 5. Auto Negotiation .................................................................................................................................................. 28
Figure 6. DA Look-Up Flowchart
1................................................................................................................................... 31
Figure 7. DA Resolution Flowchart
Stage 2.....................................................................................................................32
Figure 8. KS8995MA/FQ EEPROM Configuration Timing Diagram ................................................................................... 43
Figure 9. SPI Write Data Cycle ........................................................................................................................................... 44
Figure 10. SPI Read Data Cycle........................................................................................................................................... 44
Figure 11. SPI Multiple Write ................................................................................................................................................ 45
Figure 12. SPI Multiple Read ................................................................................................................................................ 45
Figure 13. EEPROM Interface Input Receive Timing Diagram............................................................................................. 79
Figure 14. EEPROM Interface Output Transmit Timing Diagram......................................................................................... 79
Figure 15. SNI Input Timing .................................................................................................................................................. 80
Figure 16. SNI Output Timing ............................................................................................................................................... 80
Figure 17. MAC Mode MII Timing
Data Received from MII ............................................................................................... 81
Figure 18. MAC Mode MII Timing
Data Transmitted from MII ........................................................................................... 81
Figure 19. PHY Mode MII Timing
Data Received from MII................................................................................................ 82
Figure 20. PHY Mode MII Timing
Data Transmitted from MII............................................................................................ 82
Figure 21. SPI Input Timing .................................................................................................................................................. 83
Figure 22. SPI Output Timing................................................................................................................................................ 84
Figure 23. Reset Timing........................................................................................................................................................ 85
Figure 24. Recommended Reset Circuit............................................................................................................................... 86
Figure 25. Recommended Circuit for Interfacing with CPU/FPGA Reset............................................................................. 86
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KSZ8995M 功能描述:以太網(wǎng) IC 5 Port 10/100 Switch with PHY and Frame Buffers (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8995MA 功能描述:以太網(wǎng) IC 5 Port 10/100 Switch with PHY and Frame Buffers (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8995MA4 功能描述:IC SWITCH 5-PORT 10/100 128PQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 專(zhuān)用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類(lèi)型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
KSZ8995MAB3 功能描述:IC SWITCH 5-PORT 10/100 128PQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 專(zhuān)用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類(lèi)型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
KSZ8995MA-EVAL 功能描述:以太網(wǎng)開(kāi)發(fā)工具 KSZ8995MA Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類(lèi)型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類(lèi)型:RMII 工作電源電壓:
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