參數(shù)資料
型號: KSZ8995FQ
廠商: Micrel Inc
文件頁數(shù): 71/89頁
文件大?。?/td> 0K
描述: IC SWITCH 10/100 5PORT 128-PQFP
標準包裝: 66
系列: *
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-3872-ND - BOARD EVALUATION FOR KSZ8995FQ
其它名稱: 576-3077
Micrel, Inc.
KS8995MA/FQ
October 2011
73
M9999-102611-3.0
MIB Counter Read Examples
(1) MIB counter read (read port 1 rx 64 counter)
Write to Register 110 with 0x1c (read MIB counters selected)
Write to Register 111 with 0xe (trigger the read operation)
Then,
Read Register 117 (counter value 31-24)
// If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
Read Register 118 (counter value 23-16)
Read Register 119 (counter value 15-8)
Read Register 120 (counter value 7-0)
(2) MIB counter read (read port 2 rx 64 counter)
Write to Register 110 with 0x1c (read MIB counter selected)
Write to Register 111 with 0x2e (trigger the read operation)
Then,
Read Register 117 (counter value 31-24)
//If bit 31 = 1, there was a counter overflow
//If bit 30 = 0, restart (reread) from this register
Read Register 118 (counter value 23-16)
Read Register 119 (counter value 15-8)
Read Register 120 (counter value 7-0)
(3) MIB counter read (read port 1 tx drop packets)
Write to Register 110 with 0x1d
Write to Register 111 with 0x00
Then,
Read Register 119 (counter value 15-8)
Read Register 120 (counter value 7-0)
Note:
To read out all the counters, the best performance over the SPI bus is (160+3) × 8 × 200 = 260ms, where there are 160 registers, 3 overhead, 8 clocks
per access, at 5MHz. In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the counters at
least every 30 seconds. The per port MIB counters are designed as “read clear.” A per port MIB counter will be cleared after it is accessed. All port
dropped packet MIB counters are not cleared after they are accessed. The application needs to keep track of overflow and valid conditions on these
counters.
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