參數(shù)資料
型號(hào)： KSZ8863RLL-EVAL
廠(chǎng)商： Micrel Inc
文件頁(yè)數(shù)： 26/106頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8863RLL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8863RLL
已供物品： 板
相關(guān)產(chǎn)品： 576-3752-ND - IC ETHERNET SWITCH 3PORT 48-LQFP
576-3578-ND - IC ETHERNET SW 3PORT 48-LQFP
其它名稱(chēng)： 576-3868
PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 25
4.0
TIMER0 MODULE
The Timer0 module timer/counter has the following fea-
tures:
8-bit timer/counter
Readable and writable
Internal or external clock select
Edge select for external clock
8-bit software programmable prescaler
Interrupt on overow from FFh to 00h
Figure 4-1 is a simplied block diagram of the Timer0
module.
Additional information on timer modules is available in
the PICmicro Mid-Range MCU Reference Manual,
DS33023.
4.1
Timer0 Operation
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the
Timer0
Source
Edge
Select
bit
T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
Additional information on external clock requirements
is available in the PICmicro Mid-Range MCU Refer-
ence Manual, DS33023.
4.2
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to the Watch-
dog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x
....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT.
FIGURE 4-1:
TIMER0 BLOCK DIAGRAM
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
RA4/T0CKI
T0SE
0
1
0
pin
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
clocks
TMR0
PSout
(2 cycle delay)
PSout
Data bus
8
PSA
PS2, PS1, PS0
Set interrupt
ag bit T0IF
on overow
3
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