參數(shù)資料
型號： KSZ8863RLL-EVAL
廠商： Micrel Inc
文件頁數(shù)： 103/106頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8863RLL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8863RLL
已供物品： 板
相關(guān)產(chǎn)品： 576-3752-ND - IC ETHERNET SWITCH 3PORT 48-LQFP
576-3578-ND - IC ETHERNET SW 3PORT 48-LQFP
其它名稱： 576-3868
PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 95
FIGURE 13-14: A/D CONVERSION TIMING
TABLE 13-13
A/D CONVERSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
130
TAD
A/D clock period PIC16C72/LCR72
1.6
—
s
TOSC based, VREF
≥ 2.5V
PIC16LC72/LCR72
2.0
—
s
TOSC based, VREF full range
PIC16C72/LCR72
2.0
4.0
6.0
s
A/D RC Mode
PIC16LC72/LCR72
2.5
6.0
9.0
s
A/D RC Mode
131
TCNV
Conversion time
(not including S/H time) (Note 1)
—
9.5
—
TAD
132
TACQ
Acquisition time
Note 2
5*
20
—
s
The minimum time is the amplier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134
Tgo
Q4 to A/D clock start
—
TOSC/2 §
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
135
Tswc
Switching from convert
→ sample time
1.5 §
—
TAD
*
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25
°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specication ensured by design.
Note 1:
ADRES register may be read on the following TCY cycle.
Note 2:
See Section 9.1 for min conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(TOSC/2) (1)
7
6
5
4
3
2
1
0
Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP
instruction to be executed.
1 TCY
134
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