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| 型號： | KSZ8863MLLI |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 69/106頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET SWITCH 3PORT 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 控制器類型： | 以太網(wǎng)開關(guān)控制器 |
| 接口： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 配用： | 576-3867-ND - BOARD EVALUATION FOR KSZ8863MLL |
| 其它名稱： | 576-3751 |
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PIC16C72 Series
DS39016A-page 64
Preliminary
1998 Microchip Technology Inc.
10.8
Time-out Sequence
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator conguration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 10-7,
out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 10-9). This is useful for testing purposes or to
synchronize more than one PIC16CXXX family device
operating in parallel.
Table 10-5 shows the reset conditions for some special
function registers, while Table 10-6 shows the reset
conditions for all the registers.
10.9
Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON has up to
two bits, depending upon the device.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent resets to see if bit
BOR cleared, indicating a BOR occurred. The BOR bit
is a "Don’t Care" bit and is not necessarily predictable
if the Brown-out Reset circuitry is disabled (by clearing
bit BODEN in the Conguration Word).
Bit1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
TABLE 10-3
TIME-OUT IN VARIOUS SITUATIONS
TABLE 10-4
STATUS BITS AND THEIR SIGNIFICANCE
TABLE 10-5
RESET CONDITION FOR SPECIAL REGISTERS
Oscillator Congura-
tion
Power-up
Brown-out
Wake-up from
SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms +
1024TOSC
72 ms + 1024TOSC
1024TOSC
RC
72 ms
—
72 ms
—
POR
BOR
TO
PD
0
x
1
Power-on Reset
0
x
0
x
Illegal, TO is set on POR
0
x
0
Illegal, PD is set on POR
1
0
x
Brown-out Reset
1
0
1
WDT Reset
1
0
WDT Wake-up
1
u
MCLR Reset during normal operation
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Condition
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during SLEEP
000h
0001 0uuu
---- --uu
WDT Reset
000h
0000 1uuu
---- --uu
WDT Wake-up
PC + 1
uuu0 0uuu
---- --uu
Brown-out Reset
000h
0001 1uuu
---- --u0
Interrupt wake-up from SLEEP
PC + 1(1)
uuu1 0uuu
---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1:
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
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