參數資料
| 型號： | KSZ8863MLLI |
| 廠商： | Micrel Inc |
| 文件頁數： | 44/106頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET SWITCH 3PORT 48-LQFP |
| 標準包裝： | 250 |
| 控制器類型： | 以太網開關控制器 |
| 接口： | MII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 配用： | 576-3867-ND - BOARD EVALUATION FOR KSZ8863MLL |
| 其它名稱： | 576-3751 |
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PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 41
FIGURE 8-2:
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) (PIC16C72)
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7
bit0
bit 7:
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overow Detect bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
ow, the data in SSPSR register is lost. Overow can only occur in slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overow. In master operation, the overow bit is
not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overow
In I2C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t
care" in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and congures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and congures these pins as I/O port pins
In I2C mode
1 = Enables the serial port and congures the SDA and SCL pins as serial port pins
0 = Disables serial port and congures these pins as I/O port pins
In both modes, when enabled, these pins must be properly congured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge.
0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge.
In I2C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000
= SPI master operation, clock = Fosc/4
0001
= SPI master operation, clock = Fosc/16
0010
= SPI master operation, clock = Fosc/64
0011
= SPI master operation, clock = TMR2 output/2
0100
= SPI slave mode, clock = SCK pin. SS pin control enabled.
0101
= SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110
= I2C slave mode, 7-bit address
0111
= I2C slave mode, 10-bit address
1011
= I2C firmware controlled master operation (slave idle)
1110
= I2C slave mode, 7-bit address with start and stop bit interrupts enabled
1111
= I2C slave mode, 10-bit address with start and stop bit interrupts enabled
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