參數(shù)資料
型號: KSZ8851SNLI TR
廠商: Micrel Inc
文件頁數(shù): 26/80頁
文件大?。?/td> 0K
描述: IC ETHERNET CTLR 1PORT PCI 32MLF
標準包裝: 1
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應商設備封裝: 32-MLF?(5x5)
包裝: 標準包裝
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-3506-6
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
32
M9999-083109-2.0
Loopback Support
The KSZ8851SNL provides two loopback modes, one is Near-end (Remote) loopback to support for remote diagnostic of
failure at line side, and the other is Far-end (Local) loopback to support for local diagnostic of failure at host side. In
loopback mode, the speed at the PHY port will be set to 100BASE-TX full-duplex mode.
Near-end (Remote) Loopback
Near-end (Remote) loopback is conducted at PHY port 1 of the KSZ8851SNL. The loopback path starts at the PHY port’s
receive inputs (RXP/RXM), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs
(TXP/TXM).
Bit [9] of register P1SCLMD (0xF4) is used to enable near-end loopback. The ports 1 near-end loopback path is illustrated
in the following Figure 14.
Far-end (Local) Loopback
Far-end (Local) loopback is conducted at Host of the KSZ8851SNL. The loopback path starts at the host SPI FIFO write
to transmit data, wraps around at the PHY port’s PMD/PMA, and ends at the host SPI FIFO read to receive data.
Bit [14] of register P1MBCR (0xE4) is used to enable far-end loopback at host side. The host far-end loopback path is
illustrated in the following Figure 14.
Figure 14. PHY Port 1 Near-end (Remote) and Host Far-end (Local) Loopback Paths
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KSZ8851SNLTR 制造商:Micrel Inc 功能描述:
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