參數(shù)資料
型號(hào): KSZ8841-PMQL
廠商: Micrel Inc
文件頁(yè)數(shù): 25/74頁(yè)
文件大?。?/td> 0K
描述: IC MAC CTRLR 32BIT 128-PQFP
應(yīng)用說(shuō)明: AN-142 Wake-on-LAN and Wake-Up Event
標(biāo)準(zhǔn)包裝: 66
控制器類型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 1080 (CN2011-ZH PDF)
配用: 576-1633-ND - BOARD EVALUATION KSZ8841-PMQL
其它名稱: 576-2117
KSZ8841-PMQL-ND
Micrel, Inc.
KSZ8841-PMQL
October 2007
31
M9999-100407-1.5
Configuration Revision Register (CFRV Offset 08H)
The CFRV register contains the KSZ8841-PMQL revision number. The following table shows the CFRV register bit
fields.
Bit
Default
Description
31 - 24
0x02
Base Class
Indicates the network controller, and is equal to 0x2.
23 - 16
0x00
Subclass
Indicates the Fast/Gigabit Ethernet chip, and is equal to 0x00.
15 - 8
0x00
Reserved
7 - 4
0x1
Revision Number
Indicates the KSZ8841-PMQL revision number, and is equal to 0x1. This
number is incremented for subsequent revision.
3 - 0
0x0
Step Number
Indicates the KSZ8841-PMQL step number, and is equal to 0x0 (chip
revision A). This number is incremented for subsequent KSZ8841-PMQL
steps within the current revision.
Configuration Latency Timer Register (CFLT Offset 0CH)
This register configures the cache line size field and the latency timer.
The following table shows the CFLT register bit fields.
Bit
Default
Description
31 - 16
0x00
Reserved
15 - 8
0x00
Configuration Latency Timer
Specifies, in units of PCI bus clocks, the value of the latency timer of the
KSZ8841-PMQL. When the KSZ8841-PMQL asserts FRAME_N, it enables
its latency timer to count. If the KSZ8841-PMQL deserts FRAME_N prior to
count expiration, the content of the latency timer is ignored. Otherwise,
after the count expires, the KSZ8841-PMQL initiates transaction
termination as soon as its GNT_N is deserted.
7 - 0
0x00
Cache Line Size
Specifies, in unit of 32-bit words(Dword), the system cache line size.
Configuration Base Memory Address Register (CBMA Offset 10H)
The CBMA register specifies the base memory address for accessing the KSZ8841-PMQL CSRs. This register must be
initialized prior to accessing any CSR with memory access.
The following table shows the CBMA register bit fields.
Bit
Default
Description
31 - 11
0
Configuration Base Memory Address
Defines the base address assigned for mapping the KSZ8841-PMQL
CSRs.
10 - 1
0
This field value is 0 when read.
0
Memory Space Indicator
Determines that the register maps into the Memory space.
The value in this field is 0.
This is a read-only field.
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