參數(shù)資料
型號(hào): KSZ8841-PMQL
廠商: Micrel Inc
文件頁數(shù): 24/74頁
文件大?。?/td> 0K
描述: IC MAC CTRLR 32BIT 128-PQFP
應(yīng)用說明: AN-142 Wake-on-LAN and Wake-Up Event
標(biāo)準(zhǔn)包裝: 66
控制器類型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1080 (CN2011-ZH PDF)
配用: 576-1633-ND - BOARD EVALUATION KSZ8841-PMQL
其它名稱: 576-2117
KSZ8841-PMQL-ND
Micrel, Inc.
KSZ8841-PMQL
October 2007
30
M9999-100407-1.5
Bit
Type
Default
Description
24
Status
0
Data Parity Report
This bit is set when the following conditions are met:
The KSZ8841-PMQL asserts parity error PERR_N or it senses
the assertion of PERR_N by another device.
The KSZ8841-PMQL operates as a bus master for the operation
that caused the error.
Parity error response (CFCS[6]) is set.
23 - 22
Reserved
00
Reserved
21
Status
0
66MHz Capable
0 = Not 66MHz capable
20
Status
-
New Capability
Indicates whether or not the KSZ8841-PMQL implements a list of
new capabilities. When set, this bit indicates the presence of
New capabilities.
When reset, New capabilities are not implemented.
The value of this bit is loaded from the New_Cap bit in EEPROM.
19 - 9
Reserved
0x000
Reserved
8
Command
0
System Error Enable
When set, the KSZ8841-PMQL asserts system error (SERR_N)
when it detects a parity error on the address phase.
7
Reserved
0
Reserved
6
Command
0
Parity Error Response
When set, the KSZ8841-PMQL asserts fatal bus error after it
detects a parity error.
When reset, any detected parity error is ignored and the
KSZ8841-PMQL continues normal operation. Parity checking is
disabled after hardware reset.
5 - 3
Reserved
000
Reserved
2
Command
0
Master Operation
When set, the KSZ8841-PMQL is capable of acting as a bus
master.
When reset, the KSZ8841-PMQL capability to generate PCI
accesses is disabled.
For normal operation, this bit must be set.
1
Command
0
Memory Space Access
When set, the KSZ8841-PMQL responds to memory space
accesses.
When reset, the KSZ8841-PMQL does not respond to memory
space accesses.
0
Reserved
0
Reserved
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