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參數(shù)資料
| 型號： | KSZ8051RNLI TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 40/59頁 |
| 文件大小： | 0K |
| 描述： | TXRX PHY 10/T100 3.3V RMII 32QFN |
| 特色產(chǎn)品： | KSZ8051/8031/8021 Series |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | PHY 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | RMII |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | 576-3889-6 |
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2008 Microchip Technology Inc.
DS22059B-page 45
MCP414X/416X/424X/426X
7.0
DEVICE COMMANDS
The MCP4XXX’s SPI command format supports 16
memory address locations and four commands. Each
command has two modes. These are:
Normal Serial Commands
High-Voltage Serial Commands
Normal serial commands are those where the CS pin is
driven to VIL. With High-Voltage Serial Commands, the
CS pin is driven to VIHH. In each mode, there are four
possible commands. These commands are shown in
The 8-bit commands (Increment Wiper and Decre-
commands) contain a Command Byte,
see Figure 7-1, while 16-bit commands (Read Data
and Write Data commands) contain a Command Byte
and a Data Byte. The Command Byte contains two data
bits, see Figure 7-1.
Table 7-2 shows the supported commands for each
memory location and the corresponding values on the
SDI and SDO pins.
Table 7-3 shows an overview of all the SPI commands
and their interaction with other device features.
7.1
Command Byte
The Command Byte has three fields, the Address, the
Command, and 2 Data bits, see Figure 7-1. Currently
only one of the data bits is defined (D8). This is for the
Write command.
The device memory is accessed when the master
sends a proper Command Byte to select the desired
operation. The memory location getting accessed is
contained in the Command Byte’s AD3:AD0 bits. The
action desired is contained in the Command Byte’s
C1:C0 bits, see Table 7-1. C1:C0 determines if the
desired memory location will be read, written,
Incremented (wiper setting +1) or Decremented (wiper
setting -1). The Increment and Decrement commands
are only valid on the volatile wiper registers, and in
High Voltage commands to enable/disable WiperLock
Technology and Software Write Protect.
As the Command Byte is being loaded into the device
(on the SDI pin), the device’s SDO pin is driving. The
SDO pin will output high bits for the first six bits of that
command. On the 7th bit, the SDO pin will output the
CMDERR bit state (see Section 7.3 “Error Condi-
). The 8th bit state depends on the the command
selected.
TABLE 7-1:
COMMAND BIT OVERVIEW
FIGURE 7-1:
General SPI Command Formats.
C1:C0
Bit
States
Command
# of
Bits
Operates on
Volatile/
Non-Volatile
memory
11
Read Data
16-Bits Both
00
Write Data
16-Bits Both
01
Increment (1)
8-Bits
Volatile Only
10
Decrement (1)
8-Bits
Volatile Only
Note 1:
High Voltage Increment and Decrement
commands on select non-volatile memory
locations
enable/disable
WiperLock
Technology and the software Write
Protect feature.
A
D
3
A
D
2
A
D
1
A
D
0
C
1
C
0
D
9
D
8
Memory
Command Byte
Data
Address
Bits
Command
Bits
A
D
3
A
D
2
A
D
1
A
D
0
C
1
C
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Memory
16-bit Command
Data
Address
Bits
Command
Bits
0 0 = Write Data
0 1 = INCR
1 0 = DECR
1 1 = Read Data
C C
1 0
Command
Bits
8-bit Command
Command Byte
Data Byte
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