參數(shù)資料
型號: KSZ8041MLL
廠商: Micrel Inc
文件頁數(shù): 56/65頁
文件大?。?/td> 0K
描述: TXRX 10/100 3.3V PHY MII 48-LQFP
標(biāo)準(zhǔn)包裝: 250
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: MII
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 1080 (CN2011-ZH PDF)
其它名稱: 576-3502
Micrel, Inc.
KSZ8041TL/FTL/MLL
December 2009
6
M9999-120909-1.2
List of Figures
Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 24
Figure 2. SMII Transmit Data/Control Segment................................................................................................................... 30
Figure 3. SMII Receive Data/Control Segment.................................................................................................................... 31
Figure 4. Typical Straight Cable Connection ....................................................................................................................... 32
Figure 5. Typical Crossover Cable Connection ................................................................................................................... 33
Figure 6. 25MHz Crystal / Oscillator Reference Clock for MII Mode ................................................................................... 35
Figure 7. 50MHz Oscillator Reference Clock for RMII Mode............................................................................................... 35
Figure 8. 125MHz Oscillator Reference Clock for SMII Mode ............................................................................................. 35
Figure 9. KSZ8041TL/FTL/MLL Power and Ground Connections....................................................................................... 36
Figure 10. KSZ8041TL/MLL and KSZ8041FTL Back-to-Back Media Converter................................................................. 38
Figure 11. MII SQE Timing (10Base-T) ............................................................................................................................... 50
Figure 12. MII Transmit Timing (10Base-T) ......................................................................................................................... 51
Figure 13. MII Receive Timing (10Base-T) .......................................................................................................................... 52
Figure 14. MII Transmit Timing (100Base-TX)..................................................................................................................... 53
Figure 15. MII Receive Timing (100Base-TX)...................................................................................................................... 54
Figure 16. RMII Timing – Data Received from RMII ............................................................................................................ 55
Figure 17. RMII Timing – Data Input to RMII ....................................................................................................................... 55
Figure 18. SMII Timing – Data Received from SMII ............................................................................................................ 56
Figure 19. SMII Timing – Data Input to SMII........................................................................................................................ 56
Figure 20. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 57
Figure 21. MDC/MDIO Timing.............................................................................................................................................. 58
Figure 22. Reset Timing....................................................................................................................................................... 59
Figure 23. Recommended Reset Circuit.............................................................................................................................. 60
Figure 24. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ..................................................... 60
Figure 25. Reference Circuits for LED Strapping Pins......................................................................................................... 61
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