參數(shù)資料
型號: KSZ8041MLL
廠商: Micrel Inc
文件頁數(shù): 23/65頁
文件大?。?/td> 0K
描述: TXRX 10/100 3.3V PHY MII 48-LQFP
標(biāo)準(zhǔn)包裝: 250
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: MII
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 1080 (CN2011-ZH PDF)
其它名稱: 576-3502
Micrel, Inc.
KSZ8041TL/FTL/MLL
December 2009
3
M9999-120909-1.2
Revision History
Revision
Date
Summary of Changes
1.0
12/21/06
Data sheet created.
1.1
4/27/07
Added maximum MDC clock speed.
Added 40K +/-30% to note 1 of Pin Description and Strapping Options tables for internal pull-ups/pull-
downs.
Changed Model Number in Register 3h – PHY Identifier 2.
Changed polarity (swapped definition) of DUPLEX strapping pin.
Removed DUPLEX strapping pin update to Register 4h – Auto-Negotiation Advertisement bits [8, 6].
Added Back-to-Back mode for KSZ8041TL.
Added Symbol Error to MII/RMII Receive Error description and Register 15h – RXER Counter.
Added a 100pF capacitor on REXT (pin 16) in Pin Description table.
1.2
12/9/09
Updated Ordering Information.
Changed MDIO hold time (min) from 10ns to 4ns.
Added thermal resistance ( JC).
Added chip maximum current consumption.
Added LED drive current.
Renamed Register 3h bits [3:0] to “manufacturer’s revision number” and changed default value to
“Indicates silicon revision.”
Updated RMII output delay for CRSDV and RXD[1:0] output pins.
Added support for Asymmetric PAUSE in register 4h bit [11].
Added control bits for 100Base-TX preamble restore (register 14h bit [7]) and 10Base-T preamble
restore (register 14h bit [6]).
Changed strapping pin definition for CONFIG[2:0] = 100 from “PCS Loopback” to “MII 100Mbps
Preamble Restore.”
Corrected MII timing for tRLAT, tCRS1, tCRS2.
Added SMII timing.
Added KSZ8041MLL device and updated entire data sheet accordingly.
Added 48-Pin LQFP package information.
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