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參數(shù)資料
| 型號： | KS8999I |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 21/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH 9-PORT 10/100 208-PQFP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | * |
| 類型： | * |
| 應(yīng)用： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-MQFP，208-PQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 包裝： | 散裝 |
| 配用： | 576-1023-ND - BOARD EVAL EXPERIMENT FOR KS8999 |
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KS8999
Micrel
KS8999
28
January 2005
EEPROM Operation
The EEPROM interface utilizes 2 pins that provide a clock and a serial data path. As part of the initialization sequence, the
KS8999 reads the contents of the EEPROM and loads the values into the appropriate registers. Note that the first two bytes
in the EEPROM must be “55” and “99” respectively for the loading to occur properly. If these first two values are not correct,
all other data will be ignored.
Data start and stop conditions are signaled on the data line as a state transition during clock high time. A high to low transition
indicates start of data and a low to high transition indicates a stop condition. The actual data that traverses the serial line
changes during the clock low time.
The KS8999 EEPROM interface is compatible with the Atmel AT24C01A part. Address A0, A1 and A2 are fixed to 000. Further
timing and data sequences can be found in the Atmel AT24C01A specification.
Optional CPU Interface
Instead of using an EEPROM to program the KS8999, one can use an external processor. To utilize this feature, the CFGMODE
pin (only available on the 208 pin package) needs to pulled low. This makes the KS8999 serial and clock interface into a slave
rather than a master. In this mode, clock and data are sourced from the processor.
Due to timing constraints, the maximum clock speed that the processor can generate is 8MHz. Data timing is referenced to
the rising edge of the clock and are 10ns for setup and 60ns for hold. The processor needs to supply the exact number of clock
cycles and data bits to program the KS8999 properly. KS8999 won’t start until all of the registers are programmed. Bits are
loaded from high order (bit 7) to low order (bit 0) starting with register 0 and finishing with register 53.
Register 0:
Skip clock on first bit 7
SCL clock cycle: 7
Register 1 to Register 53: provide clock on bit 7 to bit 0
SCL clock cycle: 424
Total SCL clock cycle: 431
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
SCL
SDA
Register 0
Register 1
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