參數(shù)資料
型號(hào): KS8995MI
廠商: Micrel Inc
文件頁(yè)數(shù): 55/73頁(yè)
文件大小: 0K
描述: IC SWITCH 10/100 5PORT 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
類(lèi)型: *
應(yīng)用: *
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 散裝
其它名稱: 576-1020
December 2003
59
M9999-120403
KS8995M
Micrel
(2) MIB counter read (read port 2 rx 64 counter)
Write to reg110 with 0x1c
(read MIB counter selected)
Write to reg111 with 0x2e
(trigger the read operation )
Then
Read reg117 (counter value 31-24)
// If bit 31 = 1, there was a counter overflow.
// If bit 30 = 0, restart (reread) from this register.
Read reg118 (counter value 23-16)
Read reg119 (counter value 15-8)
Read reg120 (counter value 7-0)
(3) MIB counter read (read port 1 tx drop packets)
Write to reg 110 with 0x1d
Write to reg 111 with 0x00
Then
Read reg119 (counter value 15-8)
Read reg120 (counter value 7-0)
Note:
To read out all the counters, the best performance over the SPI bus is (160+3)
× 8 × 200 = 260ms, where there are 160 register, 3 overhead, 8 clocks
per access, at 5MHz. In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the counters at
least every 30 seconds. The per port MIB counters are designed as “read clear.” A per port MIB counter will be cleared after it is accessed. All port
dropped packet MIB counters are not cleared after they are accessed. The application needs to keep track of overflow and valid conditions on these
counters.
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