參數(shù)資料
型號: KS8993FL
廠商: Micrel Inc
文件頁數(shù): 42/99頁
文件大?。?/td> 0K
描述: IC CONV MED 10/100 SGL 128PQFP
標準包裝: 66
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 管件
配用: 576-1012-ND - BOARD EVAL EXPERIMENT KS8993F
KS8993F
Micrel
August 26, 2004
Revision 1.0
- 47 -
3
MII Management (MIIM) Registers
The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I2C and SMI interfaces
can also be used to access these registers. The latter three interfaces use a different mapping mechanism than the
MIIM interface.
As defined in the IEEE 802.3 specification, the “PHYAD” are assigned as “0x1” for PHY port 1 and “0x2” for PHY port
2. The “REGAD” supported are 0,1,2,3,4 and 5. When the switch is in “center side media converter mode”. only PHY
port 1 is accessible after the PHYAD is programmed via the SPI, I2C or SMI interface.
Register Number
Description
0x0
Basic Control Register
0x1
Basic Status Register
0x2
Physical Identifier I
0x3
Physical Identifier II
0x4
Auto-Negotiation Advertisement Register
0x5
Auto-Negotiation Link Partner Ability Register
0x6 – 0x1F
Not supported
Register 0: MII Basic Control
Bit
Name
R/W
Description
Default
Reference
15
Soft reset
RO
NOT SUPPORTED
0
14
Loop back
R/W
NOT SUPPORTED
0
13
Force 100
R/W
=1, 100 Mbps
=0, 10 Mbps
0
Reg. 28, bit 6
Reg. 44, bit 6
12
AN enable
R/W
=1, Auto-Negotiation enabled
=0, Auto-Negotiation disabled
1
11
Power down
R/W
=1, power down
=0, normal operation
0
Reg. 29, bit 3
Reg. 45, bit 3
10
Isolate
RO
NOT SUPPORTED
0
9
Restart AN
R/W
=1, restart Auto-Negotiation
=0, normal operation
0
Reg. 29, bit 5
Reg. 45, bit 5
8
Force full
duplex
R/W
=1, full duplex
=0, half duplex
0
Reg. 28, bit 5
Reg. 44, bit 5
7
Collision test
RO
NOT SUPPORTED
0
6
Reserved
RO
0
5
Reserved
RO
0
4
Force MDI
R/W
=1, force MDI (transmit on RXP/RXM pins)
=0, normal operation (transmit on TXP/TXM pins)
0
Reg. 29, bit 1
Reg. 45, bit 1
3
Disable MDI-X
R/W
=1, disable auto MDI/MDI-X
=0, normal operation
0
Reg. 29, bit 2
Reg. 45, bit 2
2
Disable Far-
End fault
R/W
=1, disable Far-End fault detection
=0, normal operation
0
Reg. 29, bit 4
1
Disable
transmit
R/W
=1, disable transmit
=0, normal operation
0
Reg. 29, bit 6
Reg. 45, bit 6
0
Disable LED
R/W
=1, disable LED
=0, normal operation
0
Reg. 29, bit 7
Reg. 45, bit 7
Register 1: MII Basic Status
Bit
Name
R/W
Description
Default
Reference
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