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參數(shù)資料
| 型號： | KS8808A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | PLL Frequency Synthesizer for Pager(呼機的鎖相環(huán)頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成傳呼機（呼機的鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 91K |
| 代理商： | KS8808A |
KS8808A
PLL Frequency Synthesizer for Pager
TEL-98-D001-R1
Jan 1998
Preliminary
PIN DESCRIPTION (
Continued
)
Pin No.
Symbol
Description
6
Vss
Lock detector is also an output of the Phase Detector .
The Low state of this output shows unlock status, which is the error
width between the Ref. signal and the VCO output signal
P
LDT
10
16
NC
These pins are controlled by
A
-controller and it also has Schmitt
Trigger architecture .
The features of these pins are as follows ;
Clock input for 17 - bit Shift Register,
Serial data input ( it includes FnFr - on / off and FRC ), and
Latch enable input ( User selectable EN1 or EN2 ).
Ground terminal
Fin
7
Input terminal for 16 bit Divider from VCO.
Mostly, VCO output should be input through the AC coupling and
the minimum input level is 500 mV
P-P
( in case of 90 MHz ).
V
DD1
8
Voltage supply terminal for Oscillator and Fin block.
This pin can be supplied up to 0.95 ~ 2.0 V from Vss.
NC
9
No Connection
CLK
11
14
Fn
Output terminal for divider value of N -counter. To control the output
On/Off, the FnFr bit of the Reference register can be programmed.
When FnFr bit is set to High , this output shows low level .
15
Fr
I/O
-
I
-
-
O
I
O
O
Output terminal for divider value of R -Counter. To control the output
On/Off, the FnFr bit of the Reference register can be programmed.
When FnFr bit is set to High , this output shows low level .
I
I
DATA
EN
12
13
4
No Connection. ( pull-up )
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